Semi-analog FIR filter with high impedance state

• US 9,647,640 B2
• Filed: 07/02/2015
• Issued: 05/09/2017
• Est. Priority Date: 07/03/2014
• Status: Active Grant

• Current Assignee: ESS Technology Incorporated (Semiconductor Holding Corp.)
• Original Assignee: ESS Technology Incorporated (Semiconductor Holding Corp.)
• Inventors: Mallinson, A. Martin
• Primary Examiner(s): Malzahn, David H
• Application Number:
  US14/790,448
• Publication Number:
  US 20160006416A1
• Time in Patent Office: 677 Days
• Field of Search: None
• CPC Class Codes: H03H 15/02 using analogue shift registers

Abstract

A system and method is disclosed for placing some of the elements of a FIR filter into a high impedance state in certain situations. When it is detected that the signal to an impedance element is the same as the previous value, then the driver of that impedance element is “turned off” or goes into a high impedance state, so that no current flows through that impedance element, and it no longer contributes to the filter output. Alternatively, if the impedance elements are the same between two adjacent taps of the delay line, the driver of one of those impedance elements may be turned off or go into a high impedance state. The technique may be particularly useful in differential output filters. Turning off a driver effectively removes the attached impedance element from the filter and reduces current flow and power consumption, thus extending battery life in mobile devices.

Claims

1. A finite impulse response filter comprising:

an input configured to receive an input signal;

a delay line comprising a plurality of delay elements in series and connected to the input for propagating and delaying the input signal;

a plurality of buffers, each buffer in the plurality of buffers coupled to the delay line after a separate one of the plurality of delay elements so as to receive the delayed input signal after the input signal has passed through the connected delay element;

a plurality of control elements, each control element in the plurality of control elements coupled to a separate one of the plurality of buffers and configured to detect the delayed input signal immediately before and after the delay element to which the buffer is coupled and cause the buffer connected to the control element to not pass the delayed input signal through the buffer if the delayed input signal immediately before the delay element to which the buffer is coupled is the same as the delayed input signal after the same delay element;

a plurality of impedance elements having impedance values, each of the plurality of impedance elements coupled to a different one of the plurality of buffers than each other impedance element in the plurality of impedance elements so as to receive a delayed input signal when the connected buffer passes the delayed input signal and provide an output weighted by the impedance value of the impedance element, the impedance values of the plurality of impedance elements selected such that the sum of the outputs of the plurality of impedance elements produces a selected frequency response to the input signal; and

an output coupled to the plurality of impedance elements to produce an output signal.

2. The finite impulse response filter of claim 1 wherein the control elements coupled to the buffers and configured to cause the connected buffers to not pass the delayed input signal through the buffer comprise switches connected between the delay line and the buffers, each of the switches having a closed position which passes the signal from the delay line to the connected buffer and an open position which does not pass the signal from the delay line to the connected buffer and caused to open so that no signal is passed from the delay line to the buffer when the delayed input signal immediately before the delay element to which the buffer is coupled is the same as the delayed input signal after the same delay element.

3. The finite impulse response filter of claim 2 further comprising a controller for detecting the delayed input signal immediately before and after each delay element and causing the switch connected to a buffer to open so as to not pass the delayed input signal to the buffer if the delayed input signal immediately before a delay element is the same as the delayed input signal after the same delay element.

4. The finite impulse response filter of claim 1 wherein:

each of the buffers is configured to be placed in a high impedance state based upon a control signal such that the buffer does not pass a signal from the delay line to the connected impedance element; and

the control elements are exclusive-or gates, each exclusive-or gate having one input connected to the delay line immediately before a separate one of the delay elements and another input connected to the delay line immediately after the same separate one of the delay elements, and an output connected to a separate one of the buffers, the output of each exclusive-or gate being the control signal for the buffer connected to that exclusive-or gate which causes the buffer to be placed in a high impedance state when the delayed input signal immediately before the delay element to which the buffer is coupled is the same as the delayed input signal after the same delay element.

5. The finite impulse response filter of claim 1 further comprising a device connected to the output for limiting the bandwidth of the output signal.

6. The finite impulse response filter of claim 1 wherein the device connected to the output is a capacitor.

7. The finite impulse response filter of claim 1 wherein the impedance elements are resistors.

8. The finite impulse response filter of claim 1 wherein the impedance elements are capacitors.

9. The finite impulse response filter of claim 1 wherein the impedance elements are inductors.

10. A finite impulse response filter having a differential output for providing a first output signal and a second output signal which is the complement of the first output signal, comprising:

an input configured to receive an input signal;

a delay line comprising a plurality of delay elements in series and connected to the input for propagating and delaying the input signal;

a plurality of buffers, each buffer in the plurality of buffers coupled to the delay line after a separate one of the plurality of delay elements so as to receive the delayed input signal after the input signal has passed through the coupled delay element, configured to either provide the delayed input signal and an inverted delayed input signal as outputs or to be placed in a state in which there is no output, in response to a control signal;

first and second pluralities of impedance elements having impedance values, the impedance values of the first set of impedance elements being the same as the impedance values of the second set of impedance elements, the impedance values of the each plurality of impedance elements selected such that the sum of the outputs of each plurality of impedance elements produces a signal of a selected frequency response to the input signal,

each of the first plurality of impedance elements and each of the second plurality of impedance elements coupled to a different one of the plurality of buffers than each other impedance element in the first and second pluralities of impedance elements to receive the delayed input signal,

two impedance elements having the same impedance values being coupled to each buffer, the one from the first plurality of impedance elements receiving the delayed input signal from the buffer and the one from the second plurality of impedance elements receiving the inverted delayed input signal,

an output connected to the first plurality of impedance elements to produce a first output signal; and

an output connected to the second plurality of impedance elements to produce a second output signal which is the complement of the first output signal.

11. The finite impulse response filter of claim 10 further comprising a control element for detecting whether the impedance elements coupled to a first buffer have the same impedance values as the impedance elements connected to a second immediately successive buffer, and placing the second buffer in a state in which it does not provide the delayed input signal and inverted delayed input signal as outputs if the two buffers are coupled to impedance elements having the same impedance values.

12. The finite impulse response filter of claim 10 further comprising a control element configured to determine that the impedance elements coupled to a first buffer have the same impedance values as the impedance elements connected to the immediately successive buffer and causing the second buffer to not provide the delayed input signal and inverted delayed input signal as outputs.

13. A method of designing a finite impulse response filter having a delay line containing a plurality of delay elements and providing a differential output, comprising:

receiving at a processor a selected frequency response for the filter;

calculating by the processor an impedance value for each of a first plurality of impedance elements, each impedance element from the first plurality of impedance elements to be coupled to the delay line after a different delay element than each other impedance element in the first plurality of impedance elements so as to receive a delayed input signal and provide an output weighted by the impedance value of the impedance element, the impedance values of the first plurality of impedance elements calculated such that a sum of the outputs of the first plurality of impedance elements is a first output signal of the selected frequency response;

determining by the processor whether the first plurality of impedance elements contains two adjacent impedance elements having the same impedance values, and, if so, preventing the second such impedance element from the first plurality of impedance elements from contributing to the first output signal such that the remaining impedance elements in the first plurality of impedance elements create an adjusted first plurality of impedance elements;

connecting by the processor the outputs of the adjusted first plurality of impedance elements to provide an output signal;

determining by the processor a second plurality of impedance elements having the same impedance values as the adjusted first plurality of impedance elements to be coupled to the delay line with the same impedance values after the same delay elements but receiving an inverted delayed input signal; and

connecting by the processor the outputs of the second plurality of impedance elements to provide a signal which is the complement of the output signal.