Cooperative flash memory control
First Claim
1. A memory controller to interact with a memory having at least one memory array, the at least one memory array having physical storage locations, the memory controller comprising:
- at least one interface to receive memory commands from a host and to exchange data in association with the memory commands between a host and the at least one memory array;
logic operable to store in a management table information for every physical storage location of the at least one memory array, the information for each physical storage location representing at least one of operability of memory cells within the physical storage location, wear of memory cells within the physical storage location, period since last programming of valid data within the physical storage location, or validity status of any data stored within the physical storage location; and
logic operable to send to a host information regarding at least one of the physical storage locations of the at least one memory array in dependence on the information retained in the management table;
where the information to be sent to the host by the logic operable to send includes at least one ofstate of the at least one of the physical storage locations of the at least one memory array, wherein the state is not data values stored in the at least one memory array, oran identification of one or more addresses corresponding to at least one of the physical storage locations that match a particular state condition.
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Accused Products
Abstract
This disclosure provides for host-controller cooperation in managing NAND flash memory. The controller maintains information for each erase unit which tracks memory usage. This information assists the host in making decisions about specific operations, for example, initiating garbage collection, space reclamation, wear leveling or other operations. For example, metadata can be provided to the host identifying whether each page of an erase unit has been released, and the host can specifically then command each of consolidation and erase using direct addressing. By redefining host-controller responsibilities in this manner, much of the overhead association with FTL functions can be substantially removed from the memory controller, with the host directly specifying physical addresses. This reduces performance unpredictability and overhead, thereby facilitating integration of solid state drives (SSDs) with other forms of storage. The disclosed techniques are especially useful for direct-attached and/or network-attached storage.
107 Citations
36 Claims
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1. A memory controller to interact with a memory having at least one memory array, the at least one memory array having physical storage locations, the memory controller comprising:
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at least one interface to receive memory commands from a host and to exchange data in association with the memory commands between a host and the at least one memory array; logic operable to store in a management table information for every physical storage location of the at least one memory array, the information for each physical storage location representing at least one of operability of memory cells within the physical storage location, wear of memory cells within the physical storage location, period since last programming of valid data within the physical storage location, or validity status of any data stored within the physical storage location; and logic operable to send to a host information regarding at least one of the physical storage locations of the at least one memory array in dependence on the information retained in the management table; where the information to be sent to the host by the logic operable to send includes at least one of state of the at least one of the physical storage locations of the at least one memory array, wherein the state is not data values stored in the at least one memory array, or an identification of one or more addresses corresponding to at least one of the physical storage locations that match a particular state condition. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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24. A memory controller to interact with a memory having at least one memory array, the at least one memory array having physical storage locations, the memory controller comprising:
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means for receiving memory commands from a host and for exchanging data in association with the memory commands between a host and the memory array; means for storing, in a management table accessible to the memory controller and for every physical storage location of the at least one memory array, information representing at least one of operability of memory cells within the physical storage location, wear of memory cells within the physical storage location, period since last programming of valid data within the physical storage location, or validity status of any data stored within the physical storage location; and means for sending to a host information in dependence on the information retained by the memory controller; where the information to be sent to the host by the means for sending includes at least one of state of the at least one of the physical storage locations of the at least one memory array, wherein the state is not data values stored in the at least one memory array, or an identification of one or more addresses corresponding to at least one of the physical storage locations that match a particular state condition.
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25. An apparatus, comprising:
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at least one flash memory array having physical storage locations; and a flash memory controller having at least one interface to receive memory commands from a host and to exchange data in association with the memory commands between a host and the memory array, logic operable to store, in a management table accessible to the flash memory controller and for every physical storage location of the at least one memory array, information representing at least one of operability of memory cells within the physical storage location, wear of memory cells within the physical storage location, period since last programming of valid data within the physical storage location, or validity status of any data stored within the physical storage location, and logic operable to send to a host information in dependence on the information stored in the management table; where the information to be sent to the host by the logic operable to send includes at least one of state of the at least one of the physical storage locations of the at least one memory array, wherein the state is not data values stored in the at least one memory array, or an identification of one or more addresses corresponding to at least one of the physical storage locations that match a particular state condition. - View Dependent Claims (26, 27, 28, 29, 30)
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31. A memory controller integrated circuit, comprising:
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at least one interface to receive memory commands from a host including commands to program pages of a NAND flash memory, to read physical pages of the NAND flash memory and to erase physical erase units of the NAND flash memory, where the NAND flash memory comprises physical storage locations that are each an integer number of at least one of (a) one or more physical pages of the NAND flash memory and (b) one or more physical erase units of the NAND flash memory; logic operable to store, in a management table accessible to the memory controller integrated circuit and for at least each erase unit of the NAND flash memory, information representing at least one of operability of memory cells within the physical storage location, wear of memory cells within the physical storage location, period since last programming of valid data within the physical storage location, or validity status of any data stored within the physical storage location; and logic operable to service host queries dependent on the information stored in the management table, and to transmit responsive information to a host; where the responsive information to be sent to the host by the logic operable to service includes at least one of state of the at least one of the physical storage locations of the at least one memory array, wherein the state is not data values stored in the at least one memory array, or an identification of address corresponding to at least one of the physical storage locations that match a particular state condition. - View Dependent Claims (32, 33)
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34. A memory controller to interact with a memory having at least one memory array, the memory controller comprising:
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at least one interface to receive memory commands from a host and to exchange data in association with the memory commands between a host and the memory array; logic operable to store in a management table information for every physical storage location of the at least one memory array, the information for each physical storage location representing page release status for each page of memory cells associated with the respective physical storage location; and logic operable to send to a host information regarding at least one of the physical storage locations of the memory array in dependence on the page release status information retained in the management table; where the information to be sent to the host by the logic operable to send includes at least one of state of the at least one of the physical storage locations of the at least one memory array, wherein the state is not data values stored in the at least one memory array, or an identification of one or more addresses corresponding to at least one of the physical storage locations that match a particular state condition. - View Dependent Claims (35, 36)
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Specification