Multi-threaded low-level startup for system boot efficiency

• US 9,658,858 B2
• Filed: 10/16/2013
• Issued: 05/23/2017
• Est. Priority Date: 10/16/2013
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Koszek, Wojciech A.
• Primary Examiner(s): Butler, Dennis M
• Application Number:
  US14/055,826
• Publication Number:
  US 20150106609A1
• Time in Patent Office: 1,315 Days
• CPC Class Codes: G06F 9/4401 Bootstrapping security arrangements therefor G06F21/57
• CPC Class Codes: G06F 9/4405 Initialisation of multiprocessor systems

Abstract

Methods, computer-readable media and devices for executing a plurality of startup instructions are disclosed. For example, a method includes a first processor of a device accessing a plurality of startup instructions in response to a startup of the device. The first processor then executes a first startup instruction of the plurality of startup instructions to perform a first task and executes a second startup instruction of the plurality of startup instructions. The executing the second startup instruction causes the first processor to send a further instruction to a second processor of the device to perform a second task. At least a portion of the first task and at least a portion of the second task are performed at a same time.

Claims

1. A method for executing a plurality of startup instructions for a device, the method comprising:

accessing, by a first processor of the device, a first startup instruction of the plurality of startup instructions using an address hard coded in the first processor, wherein accessing the first startup instruction is performed in response to a startup of the device;

executing, by the first processor, the first startup instruction of the plurality of startup instructions to perform a first task;

accessing, by a second processor of the device, a second startup instruction of the plurality of startup instructions using an address hard coded in the second processor, wherein accessing the second startup instruction is performed in response to the startup of the device; and

executing, by the second processor, the second startup instruction of the plurality of startup instructions to perform a second task, wherein at least a portion of the first task and at least a portion of the second task are performed at a same time.

2. The method of claim 1, wherein the plurality of startup instructions is stored in a non-volatile memory of the device.

3. The method of claim 1, wherein the plurality of startup instructions is stored in a volatile memory of the device.

4. The method of claim 1, wherein the first task comprises:

performing a power on self test of the device.

5. The method of claim 1, wherein the first task comprises:

retrieving a programmable logic image from a storage device; and

writing the programmable logic image to a programmable logic portion of the device.

6. The method of claim 1, wherein accessing the first startup instruction of the plurality of startup instructions comprises:

retrieving the first startup instruction of the plurality of startup instructions starting at a particular memory location of a non-volatile memory of the device, wherein an address of the particular memory location is stored in a register of the first processor and is accessed by the first processor at the startup of the device.

7. The method of claim 1, wherein the first or the second task comprises:

initializing at least a portion of a volatile memory of the device, wherein the initializing the at least a portion of the volatile memory comprises writing a known pattern to the volatile memory.

8. The method of claim 1, wherein the second task comprises at least one of:

retrieving a programmable logic image from a storage device of the device;

or

writing the programmable logic image to a programmable logic portion of the device.

9. The method of claim 1, wherein the plurality of startup instructions comprises a boot loader program.

10. The method of claim 1, wherein the first task comprises at least one of:

decompressing a boot loader program that is retrieved from a non-volatile memory or a storage device of the device;

authenticating the boot loader program;

or

decrypting the boot loader program.

11. The method of claim 10, wherein the authenticating comprises:

accessing a hash signature from a storage device of the device; and

verifying an integrity of the boot loader program using the hash signature.

12. The method of claim 10, wherein the decrypting comprises:

accessing a decryption key from a storage device of the device; and

decrypting the boot loader program using the decryption key.

13. The method of claim 1, wherein the startup of the device comprises a power-on event or a reset event.

14. The method of claim 1, wherein the same time comprises a time prior to the device operating a first stage boot loader.

15. A non-transitory computer-readable medium storing a plurality of startup instructions which, when executed by a first processor of a device, cause the first processor to perform operations, the operations comprising:

performing a first task comprising an initialization of a memory, in response to a startup of the device; and

sending a further instruction to a second processor of the device to perform a second task, wherein;

at least a portion of the first task and at least a portion of the second task are performed at a same time; and

the second task comprises writing a programmable logic image to a programmable logic portion of the device.

16. The non-transitory computer-readable medium of claim 15, wherein the programmable logic portion of the device comprises a field programmable gate array (FPGA).

17. An apparatus comprising:

a first processor;

a second processor; and

a non-transitory computer-readable medium storing a plurality of startup instructions, wherein;

the first processor is configured to access a first startup instruction of the plurality of startup instructions using an address hard coded in the first processor in response to a startup of the apparatus and to execute the first startup instruction to perform a first task;

the second processor is configured to access a second startup instruction of the plurality of startup instructions using an address hard coded in the second processor in response to the startup of the apparatus and to execute the second startup instruction to perform a second task; and

the first processor and the second processor are configured to perform at least a portion of the first task and at least a portion of the second task at a same time.

18. The apparatus of claim 17, further comprising a storage device, wherein the second task comprises at least one of:

retrieving a programmable logic image from the storage device;

or

writing the programmable logic image to a programmable logic portion of the apparatus.

19. The apparatus of claim 17, further comprising a non-volatile memory, wherein the first processor is configured to access the first startup instruction by retrieving the first startup instruction starting at a particular memory location of the non-volatile memory, wherein an address of the particular memory location is stored in a register of the first processor and is accessed by the first processor at the startup of the apparatus.

20. The apparatus of claim 17, further comprising a volatile memory, wherein the second task comprises initializing at least a portion of the volatile memory by writing a known pattern to the volatile memory.

21. The apparatus of claim 17, further comprising a volatile memory, wherein the plurality of startup instructions is stored in the volatile memory.