Apparatuses and methods for shifting data
First Claim
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1. An apparatus, comprising:
- a first pre-charge line;
a second pre-charge line;
a first p-channel transistor including a gate coupled to the first pre-charge line, and a first terminal coupled to a first sense line and a second terminal coupled to a first voltage supply node;
a first n-channel transistor including a gate coupled to a first control line and a terminal coupled to the first sense line;
a first inverter including an input coupled to the first sense line;
a second p-channel transistor including a gate coupled to the second pre-charge line, and a first terminal coupled to a second sense line and a second terminal coupled to a second voltage supply node;
a second n-channel transistor including a gate coupled to a second control line, a first terminal coupled to an output of the first inverter, and a second terminal coupled to the second sense line; and
a second inverter including an input coupled to the second sense line.
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Abstract
The present disclosure includes apparatuses and methods related to shifting data. A number of embodiments include an apparatus comprising pre-charge lines and n-channel transistors without complementary p-channel transistors. A number of embodiments include a method comprising shifting data by pre-charging nodes with an operating voltage.
353 Citations
20 Claims
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1. An apparatus, comprising:
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a first pre-charge line; a second pre-charge line; a first p-channel transistor including a gate coupled to the first pre-charge line, and a first terminal coupled to a first sense line and a second terminal coupled to a first voltage supply node; a first n-channel transistor including a gate coupled to a first control line and a terminal coupled to the first sense line; a first inverter including an input coupled to the first sense line; a second p-channel transistor including a gate coupled to the second pre-charge line, and a first terminal coupled to a second sense line and a second terminal coupled to a second voltage supply node; a second n-channel transistor including a gate coupled to a second control line, a first terminal coupled to an output of the first inverter, and a second terminal coupled to the second sense line; and a second inverter including an input coupled to the second sense line. - View Dependent Claims (2, 3, 4, 5, 6)
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7. An apparatus, comprising:
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an array comprising a plurality of columns of memory cells; and a controller coupled to the array and configured to; shift data from a first compute component coupled to a first column of memory cells to a second compute component coupled to a second column of memory cells; wherein, in order to shift the data, the controller is configured to; pre-charge a first node of the first compute component with an operating voltage; and pre-charge a second node of the first compute component with the operating voltage. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15)
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16. A method for shifting data from a first compute component to a second compute component, comprising:
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applying a first signal to a first pre-charge line that is coupled to a gate of a first p-channel transistor; applying a second signal to a first control line that is coupled to a gate of a first n-channel transistor; inverting a signal between the first n-channel transistor and a second n-channel transistor; applying a third signal to a second pre-charge line that is coupled to gate of a second p-channel transistor; applying a fourth signal to a second control line that is coupled to a gate of a second n-channel transistor; and inverting a signal between the second n-channel transistor and a n-channel transistor of the second compute component. - View Dependent Claims (17, 18, 19, 20)
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Specification