Method of making multi-layer electronic components with plated terminations

• US 9,666,366 B2
• Filed: 09/28/2004
• Issued: 05/30/2017
• Est. Priority Date: 04/15/2002
• Status: Active Grant

• Current Assignee: Kyocera AVX Components Corporation (Kyocera Corporation)
• Original Assignee: AVX Corporation (Kyocera Corporation)
• Inventors: Heistand, II, Robert, Ritter, Andrew P., Galvagni, John L., Dattaguru, Sriram
• Primary Examiner(s): Talbot, Brian K
• Application Number:
  US10/951,972
• Publication Number:
  US 20050046536A1
• Time in Patent Office: 4,627 Days
• Field of Search: 427 79- 81, 427305, 427402, 427437, 4274431, 29 2503, 29 2541, 29 2542
• CPC Class Codes: C23C 18/1651 Two or more layers only obtained by electroless plating
• CPC Class Codes: C23C 18/1653 Two or more layers with at least one layer obtained by electroless plating and one layer obtained by electroplating
• CPC Class Codes: C23C 18/32 Coating with nickel, cobalt or mixtures thereof with phosphorus or boron C23C18/50 takes precedence
• CPC Class Codes: C23C 18/38 Coating with copper
• CPC Class Codes: C23C 18/48 Coating with alloys
• CPC Class Codes: C23C 28/021 including at least one metal alloy layer
• CPC Class Codes: C23C 28/023 only coatings of metal elements only
• CPC Class Codes: C25D 3/56 of alloys
• CPC Class Codes: C25D 5/02 Electroplating of selected surface areas
• CPC Class Codes: C25D 5/34 Pretreatment of metallic surfaces to be electroplated
• CPC Class Codes: C25D 7/00 Electroplating characterised by the article coated
• CPC Class Codes: H01C 1/14 Terminals or tapping points or electrodes specially adapted for resistors in general H01R; Arrangements of terminals or tapping points or electrodes on resistors
• CPC Class Codes: H01C 17/28 adapted for applying terminals
• CPC Class Codes: H01C 7/008 Thermistors H01C7/02 - H01C7/06 take precedence
• CPC Class Codes: H01C 7/10 voltage responsive, i.e. varistors
• CPC Class Codes: H01F 41/04 for manufacturing coils coils for transformer or inductances H01F27/28
• CPC Class Codes: H01G 4/005 Electrodes
• CPC Class Codes: H01G 4/008 Selection of materials
• CPC Class Codes: H01G 4/012 Form of non-self-supporting electrodes
• CPC Class Codes: H01G 4/06 Solid dielectrics
• CPC Class Codes: H01G 4/12 : Ceramic dielectrics H01G4/085 takes precedence
• CPC Class Codes: H01G 4/228 : Terminals
• CPC Class Codes: H01G 4/232 : electrically connecting two or more layers of a stacked or rolled capacitor
• CPC Class Codes: H01G 4/30 : Stacked capacitors H01G4/33 takes precedence
• CPC Class Codes: H05K 2201/09709 : Staggered pads, lands or terminals; Parallel conductors in different planes
• CPC Class Codes: H05K 3/02 : in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
• CPC Class Codes: H05K 3/403 : Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof H05K3/4092 takes precedence
• CPC Class Codes: Y10T 29/42 : Piezoelectric device making
• CPC Class Codes: Y10T 29/43 : Electric condenser making
• CPC Class Codes: Y10T 29/435 : Solid dielectric type
• CPC Class Codes: Y10T 29/49002 : Electrical device making
• CPC Class Codes: Y10T 29/49099 : Coating resistive material on a base
• CPC Class Codes: Y10T 29/49101 : Applying terminal

Abstract

Improved method steps for making a multilayer electronic components are disclosed. Monolithic components are formed with plated terminations whereby the need for typical thick-film termination stripes is eliminated or greatly simplified. Such termination technology eliminates many typical termination problems and enables a higher number of terminations with finer pitch, which may be especially beneficial on smaller electronic components. Electrodes and insulating substrates are provided in an interleaved arrangement and selected portions of the electrodes are exposed along selected edges of the substrates. Anchor tabs, which are not in direct contact with the electrodes and offer additional nucleation points for plated structures, may also optionally be provided and exposed in some embodiments. Termination material is then plated to the exposed portions of the electrodes and optional anchor tabs, such as via electroless and/or electrochemical processes, until exposed portions of selected groups thereof are connected.

Claims

1. A method of making a multi-layer electronic component, comprising the steps of:

providing a plurality of insulating substrates each having an upper and a lower surface, said substrates each being delimited laterally by edges;

interleaving a plurality of electrodes between selected of said plurality of insulating substrates;

exposing selected portions of said electrodes along at least one edge of said substrates;

providing anchor tabs interleaved at selected locations between the insulating substrates and positioned such that they are not in direct contact with any of said plurality of electrodes;

exposing portions of said anchor tabs at selected edges of the insulating substrates; and

submersing the electronic component in a plating solution to deposit at least one layer of termination material directly on said exposed portions of said electrodes and on said exposed portions of said anchor tabs until the exposed portions of selected of said electrodes and anchor tabs are connected by the at least one layer of termination material;

wherein the step of plating is performed using an electroless process;

the electroless process comprises submersing the multi-layer electronic component in an electroless copper plating solution to form a copper termination layer; and

the method further comprises the step of covering the copper termination layer with a resistive layer.

2. The method of claim 1, wherein the electroless process is followed by an electrochemical process.

3. The method of claim 1, further comprising plating the resistive layer with a conductive layer.

4. A method of making a multi-layer electronic component, comprising the steps of:

providing a plurality of insulating substrates each having an upper and a lower surface, said substrates each being delimited laterally by edges;

interleaving a plurality of electrodes between selected of said plurality of insulating substrates;

exposing selected portions of said electrodes along at least one edge of said substrates;

providing anchor tabs interleaved at selected locations between the insulating substrates and positioned such that they are not in direct contact with any of said plurality of electrodes;

exposing portions of said anchor tabs at selected edges of the insulating substrates;

submersing the electronic component in a copper plating solution to deposit at least one layer of copper termination material directly on said exposed portions of said electrodes and on said exposed portions of said anchor tabs until the exposed portions of selected of said electrodes and anchor tabs are connected by the at least one layer of copper termination material; and

covering the copper termination layer with a resistive layer.

5. The method of claim 4, further comprising plating the resistive layer with a conductive layer.

6. The method of claim 4, wherein the step of plating is performed using an electroless process followed by an electrochemical process.

7. The method of claim 4, wherein the step of plating is performed using an electroless process.