Slew rate control apparatus for digital microphones

• US 9,668,051 B2
• Filed: 06/23/2016
• Issued: 05/30/2017
• Est. Priority Date: 09/04/2013
• Status: Active Grant

• Current Assignee: Knowles Electronics Llc (Knowles Corporation)
• Original Assignee: Knowles Electronics Llc (Knowles Corporation)
• Inventors: Furst, Claus Erdmann, Yurttas, Aziz, Mortensen, Anders Svava, Nielsen, John, Smith, Paul
• Primary Examiner(s): Agustin, Peter Vincent
• Application Number:
  US15/190,996
• Publication Number:
  US 20160309256A1
• Time in Patent Office: 341 Days
• Field of Search: None
• CPC Class Codes: H04R 1/04 Structural association of microphone with electric circuitry therefor in deaf-aid sets H04R25/00
• CPC Class Codes: H04R 2499/11 Transducers incorporated or for use in hand-held devices, e.g. mobile phones, PDA's, camera's
• CPC Class Codes: H04R 3/00 Circuits for transducers , loudspeakers or microphones
• CPC Class Codes: H04R 3/04 for correcting frequency response
• CPC Class Codes: H04R 3/08 of electromagnetic transducers

Abstract

A driver, includes a driver block, a controller block, and a comparison block. The driver block includes an adjustable current source configured to produce a digital output stream. The controller block is coupled to the driver block. The comparison block is coupled to the driver block and the controller block. The comparison block is configured to compare the digital output stream to a reference value at a time delayed with respect to a master clock and based upon the comparison cause the controller block to adjust a strength of the driver block.

Claims

1. A system comprising:

a digital microphone configured to convert a signal to a digital signal;

a master clock;

a driver configured to produce a digital output stream based upon the digital signal from the digital microphone, the driver comprising;

an adjustable current source;

a current source controller block; and

a comparison block to the current source controller block, and configured to compare the digital output stream to a reference value at a time delayed with respect to the master clock and based upon the comparison cause the current source controller block to adjust a strength of the driver.

2. The system of claim 1, wherein the driver further comprises an adjustable current sink.

3. The system of claim 2, further comprising a current sink controller block, wherein the current source controller is a counter, and wherein the current controller block is a counter.

4. The system of claim 1, wherein the driver further comprises asynchronous logic configured to:

receive an output of the comparison block;

determine to change the current source counter or the current sink counter based upon the output of the comparison block; and

control the current source counter or the current sink counter.

5. The driver of claim 4, wherein the current source controller block is configured to output current source control data, and

wherein the adjustable current source is configured to:

receive the current source control data; and

adjust a drive strength of the adjustable current source based upon the received current source control data.

6. The driver of claim 5, wherein the current sink controller block is configured to output current sink control data, and

wherein the adjustable current sink is configured to:

receive the current sink control data; and

adjust a drive strength of the adjustable current sink based upon the received current sink control data.

7. The driver of claim 6, wherein the digital output stream is based upon the adjusted drive strength of the adjustable current source and the adjusted drive strength of the adjustable current sink.

8. The driver of claim 3, further comprising:

a current source toggle counter configured to;

count toggles of the current source counter; and

disable the current source counter based upon a first predetermined number of toggles.

9. The driver of claim 8, further comprising:

a current sink toggle counter configured to;

count toggles of the current sink counter; and

disable the current sink counter based upon a second predetermined number of toggles.

10. The driver of claim 1, wherein the digital output stream comprises a square waveform.

11. The driver of claim 1, wherein the digital output stream comprises a modified square wave form with a slanted edge.

12. The driver of claim 1, wherein the delay represents a time desirable for the output of the driver to settle.

13. The driver of claim 1, wherein the driver strength is increased, the increase being effective to decrease a setting time of the digital output stream at a next clock.

14. The driver of claim 1, wherein the driver strength is decreased, the decrease being effective to increase a settling time of the digital output stream at a next clock.

15. A method of controlling a driver, the method comprising:

receiving, from a digital microphone, a digital signal;

comparing, by a comparator circuit of the driver, a digital output stream of a driver to a reference value at a time delayed with respect to a master clock, wherein the digital output stream of the driver is based upon the digital signal from the digital microphone; and

based upon the comparing, causing, by an asynchronous circuit of the driver, an adjustment of a strength of the driver, the strength being a capability of the driver, the adjustment being effective to alter a settling of the digital output stream.

16. The method of claim 15, further comprising:

counting a first number of counter toggles of a current source counter; and

disabling the current source counter based upon the first number of counter toggles being greater than a predetermined amount.

17. The method of claim 15, wherein the causing the adjustment of the strength of the driver comprises adjusting a drive strength of an adjustable current source.

18. The method of claim 15, wherein the causing the adjustment of the strength of the driver comprises adjusting a drive strength of an adjustable current sink.

19. The method of claim 15, wherein the delay represents a time desirable for the output of the driver to settle.

20. The method of claim 15, wherein the adjustment is an increase in the drive strength, the increase in the drive strength being effective to decrease a settling time of the digital output stream at a next clock.