Array substrate, method for manufacturing the same and display apparatus
First Claim
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1. An array substrate, comprising:
- a substrate;
a common electrode and a pixel electrode sequentially formed on the substrate and insulated from each other;
a thin film transistor comprising a gate electrode, an active layer, a source electrode and a drain electrode, wherein the drain electrode is electrically connected with the pixel electrode; and
a common electrode line disposed in a same layer as the gate electrode;
wherein the array substrate further comprises an insulating layer between the gate electrode and the common electrode to isolate the gate electrode from the common electrode, and the common electrode is connected with the common electrode line through a first through hole, andwherein the common electrode line and the gate electrode are provided on the substrate, the insulating layer is provided on the substrate and covers the common electrode line and the gate electrode, the common electrode is provided on the insulating layer, a portion of the insulating layer covering the common electrode line has the first through hole.
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Abstract
An array substrate, a method for manufacturing the same and a display apparatus are provided. The array substrate comprises: a substrate (1); a common electrode (2) and a pixel electrode (10) sequentially formed on the substrate (1) and insulated from each other; a thin film transistor comprising a gate electrode (4), an active layer (7), a source electrode (8a) and a drain electrode (8b), wherein the drain electrode (8b) is electrically connected with the pixel electrode (10); a common electrode line (5) disposed in a same layer as the gate electrode (4); and an insulating layer (3) between the gate electrode (4) and the common electrode (2), wherein the common electrode (2) is connected with the common electrode line (5) through a through hole in the insulating layer (3).
6 Citations
8 Claims
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1. An array substrate, comprising:
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a substrate; a common electrode and a pixel electrode sequentially formed on the substrate and insulated from each other; a thin film transistor comprising a gate electrode, an active layer, a source electrode and a drain electrode, wherein the drain electrode is electrically connected with the pixel electrode; and a common electrode line disposed in a same layer as the gate electrode; wherein the array substrate further comprises an insulating layer between the gate electrode and the common electrode to isolate the gate electrode from the common electrode, and the common electrode is connected with the common electrode line through a first through hole, and wherein the common electrode line and the gate electrode are provided on the substrate, the insulating layer is provided on the substrate and covers the common electrode line and the gate electrode, the common electrode is provided on the insulating layer, a portion of the insulating layer covering the common electrode line has the first through hole. - View Dependent Claims (2, 3, 4)
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5. An array substrate, comprising:
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a substrate; a common electrode and a pixel electrode sequentially formed on the substrate and insulated from each other; a thin film transistor comprising a gate electrode, an active layer, a source electrode and a drain electrode, wherein the drain electrode is electrically connected with the pixel electrode; and a common electrode line disposed in a same layer as the gate electrode; wherein the array substrate further comprises an insulating layer between the gate electrode and the common electrode to isolate the gate electrode from the common electrode, and the common electrode is connected with the common electrode line through a first through hole, and wherein the common electrode line and the gate electrode are provided on the substrate, the insulating layer is provided on the substrate and covers the common electrode line and the gate electrode, the common electrode is provided on the insulating layer above the common electrode line; the array substrate further comprises a gate electrode protection layer covering the common electrode and the insulating layer; the active layer is provided on the gate electrode protection layer above the gate electrode; the source electrode and the drain electrode are provided on the active layer; the array substrate further comprises a passivation layer covering the source electrode, the drain electrode and the gate electrode protection layer; and the first through hole is provided above the common electrode line and sequentially penetrates through the passivation layer, the gate electrode protection layer, the common electrode and the insulating layer. - View Dependent Claims (6, 7, 8)
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Specification
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Current AssigneeBOE Technology Group Co., Ltd.
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Original AssigneeBeijing BOE Display Technology Co Ltd (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
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InventorsLiu, Yao, Bai, Jinchao, Li, Liangliang, Hao, Zhaohui, Sun, Liang
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Primary Examiner(s)McCall Shepard, Sonya D
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Application NumberUS15/177,795Publication NumberTime in Patent Office362 DaysField of Search257 59, 438 30, 349 52US Class CurrentCPC Class CodesG02F 1/133345 Insulating layers G02F1/133...G02F 1/134318 having a patterned common e...G02F 1/1345 Conductors connecting elect...G02F 1/136227 Through-hole connection of ...G02F 1/136286 Wiring, e.g. gate line, dra...G02F 1/1368 in which the switching elem...G02F 2201/121 common or backgroundG02F 2201/123 pixelG02F 2201/40 Arrangements for improving ...H01L 23/3171 the coating being directly ...H01L 27/1214 comprising a plurality of T...H01L 27/1218 with a particular compositi...H01L 27/124 with a particular compositi...H01L 27/1248 with a particular compositi...
