Active load modulation in near field communication

• US 9,673,964 B2
• Filed: 02/18/2015
• Issued: 06/06/2017
• Est. Priority Date: 02/18/2015
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Ghahramani, Mohammad Mahdi, Talwalkar, Niranjan Anand, Taghivand, Mazhareddin
• Primary Examiner(s): Ali, Shawkat M
• Application Number:
  US14/625,518
• Publication Number:
  US 20160241380A1
• Time in Patent Office: 839 Days
• Field of Search: 327148, 327154, 327156, 327159, 331 25, 331 34, 332128, 375219, 375238, 375259, 375268, 375295, 375316, 375375, 375376, 455 411, 455106
• CPC Class Codes: H04B 5/72 for local intradevice communication
• CPC Class Codes: H04L 7/0012 by comparing receiver clock with transmitter clock
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

An example method for active load modulation includes determining a modulated portion and an unmodulated portion of a bit. Further, the example method includes during the modulated portion of the bit, holding a phase of a received carrier signal. In addition, the example method includes, during the unmodulated portion of the bit, synchronizing to the received carrier signal.

Claims

1. A method for active load modulation, comprising:

receiving, at a first near field communication (NFC) device, a signal with a modulated portion and an unmodulated portion from a second NFC device, wherein the signal comprises a carrier reference signal; and

recovering, by the first NFC device, the carrier reference signal received from the second NFC device, wherein the recovering comprises;

during the modulated portion of the signal for each bit, maintaining, by the first NFC device, a phase of the received carrier reference signal; and

during the unmodulated portion of the signal for each bit, synchronizing, by the first NFC device, to the received carrier reference signal.

2. The method of claim 1, further comprising:

deter mining a phase relationship between the received carrier reference signal and a local clock signal.

3. The method of claim 2, wherein the synchronizing comprises synchronizing to the received carrier reference signal based on the determined phase relationship.

4. The method of claim 2, further comprising:

adjusting a phase of the local clock signal when the determined phase relationship indicates a mismatch.

5. The method of claim 1, wherein the synchronizing comprises synchronizing to the received carrier reference signal with a frequency substantially close to 448th harmonic of a local clock signal or a frequency substantially close to 6 GHz.

6. An apparatus for active load modulation, comprising:

a memory storing executable instructions; and

a processor in communication with the memory, wherein the processor is configured to execute the instructions to;

receive a signal with a modulated portion and an unmodulated portion, wherein the signal comprises a carrier reference signal; and

recover the received carrier reference signal, wherein the processor is further configured to execute the instructions to;

maintain a phase of the received carrier reference signal during the modulated portion of the signal for each bit; and

synchronize to the received carrier reference signal during the unmodulated portion of the signal for each bit.

7. The apparatus of claim 6, wherein the processor is further configured to execute the instructions to determine a phase relationship between the received carrier reference signal and a local clock signal.

8. The apparatus of claim 7, wherein the processor is further configured to execute the instructions to synchronize to the received carrier reference signal based on the determined phase relationship.

9. The apparatus of claim 7, wherein the processor is further configured to execute the instructions to adjust a phase of the local clock signal when the determined phase relationship indicates a mismatch.

10. The apparatus of claim 6, wherein the processor is further configured to execute the instructions to synchronize to the received carrier reference signal with a frequency substantially close to 448th harmonic of a local clock signal or a frequency substantially close to 6 GHz.

11. The apparatus of claim 6, wherein the processor is further configured to execute the instructions to activate a phase-locked loop (PLL) for recovering the received carrier reference signal.

12. The apparatus of claim 6, wherein the processor is further configured to execute the instructions to activate a phase-frequency detector (PFD) for recovering the received carrier reference signal, wherein the PFD is tri-stated.

13. An apparatus for active load modulation, comprising:

means for receiving a signal with a modulated portion and an unmodulated portion, wherein the signal comprises a carrier reference signal; and

means for recovering the received carrier reference signal, wherein the means for recovering comprises;

means for maintaining a phase of the received carrier reference signal during the modulated portion of the signal for each bit; and

means for synchronizing to the received carrier reference signal during the unmodulated portion of the signal for each bit.

14. The apparatus of claim 13, further comprising:

means for determining a phase relationship between the received carrier reference signal and a local clock signal.

15. The apparatus of claim 14, wherein the means for synchronizing comprises means for synchronizing the local clock signal to the received carrier reference signal based on the determined phase relationship.

16. The apparatus of claim 14, further comprising:

means for adjusting a phase of the local clock signal when the determined phase relationship indicates a mismatch.

17. The apparatus of claim 13, wherein the means for synchronizing comprises means for synchronizing to the received carrier reference signal with a frequency substantially close to 448th harmonic of a local clock signal or a frequency substantially close to 6 GHz.

18. A non-transitory computer-readable medium comprising instructions, that when executed by a processor, cause the processor to:

receive a signal with a modulated portion and an unmodulated portion, wherein the signal comprises a carrier reference signal; and

recover the received carrier reference signal, wherein the non-transitory computer-readable medium comprises further instructions, that when executed by the processor, cause the processor to;

maintain a phase of the received carrier reference signal during the modulated portion of the signal for each bit; and

synchronize to the received carrier reference signal during the unmodulated portion of the signal for each bit.

19. The non-transitory computer-readable medium of claim 18, wherein the non-transitory computer-readable medium comprises further instructions, that when executed by the processor, cause the processor to:

determine a phase relationship between the received carrier reference signal and a local clock signal.

20. The non-transitory computer-readable medium of claim 19, wherein the non-transitory computer-readable medium comprises further instructions, that when executed by the processor, cause the processor to:

synchronize to the received carrier reference signal based on the determined phase relationship.

21. The non-transitory computer-readable medium of claim 19, wherein the non-transitory computer-readable medium comprises further instructions, that when executed by the processor, cause the processor to:

adjust a phase of the local clock signal when the determined phase relationship indicates a mismatch.

22. The non-transitory computer-readable medium of claim 18, wherein the non-transitory computer-readable medium comprises further instructions, that when executed by the processor, cause the processor to:

synchronize to the received carrier reference signal with a frequency substantially close to 448th harmonic of a local clock signal or a frequency substantially close to 6 GHz.