Integrated RF front end with stacked transistor switch

• US 9,680,416 B2
• Filed: 10/11/2013
• Issued: 06/13/2017
• Est. Priority Date: 06/23/2004
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Cable, James S., Burgener, Mark L.
• Primary Examiner(s): TRAN, PABLO N
• Application Number:
  US14/052,680
• Publication Number:
  US 20140179249A1
• Time in Patent Office: 1,341 Days
• Field of Search: 455333, 4551273, 455341, 4551271, 4551272, 455121, 455126, 455128- 29, 455339, 330311, 330277, 330287, 330251, 330136, 330310, 330295, 330124 R, 330 10, 247341, 247280-281, 247472
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01Q 23/00 Antennas with active circuits or circuit elements integrated within them or attached to them
• CPC Class Codes: H03F 1/0205 in transistor amplifiers
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 1/56 Modifications of input or output impedances, not otherwise provided for
• CPC Class Codes: H03F 1/565 using inductive elements
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/372 Noise reduction and elimination in amplifier
• CPC Class Codes: H03F 2200/387 A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2200/61 the cascode amplifier has more than one common gate stage
• CPC Class Codes: H03F 3/189 High-frequency amplifiers, e.g. radio frequency amplifiers
• CPC Class Codes: H03F 3/19 with semiconductor devices only
• CPC Class Codes: H03F 3/21 with semiconductor devices only H03F3/245 takes precedence
• CPC Class Codes: H03F 3/2171 with field-effect devices H03F3/2173 - H03F3/2178 take precedence
• CPC Class Codes: H03F 3/68 Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602
• CPC Class Codes: H03G 11/00 Limiting amplitude; Limiting rate of change of amplitude ; Clipping in general
• CPC Class Codes: H03G 3/3042 in modulators, frequency-changers, transmitters or power amplifiers transmission power control in bidirectional transmission systems H04W52/04
• CPC Class Codes: H04B 1/0053 with common antenna for more than one band
• CPC Class Codes: H04B 1/0475 with means for limiting noise, interference or distortion H04B1/0483 takes precedence
• CPC Class Codes: H04B 1/48 : in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter H04B1/46 takes precedence
• CPC Class Codes: H04L 27/04 : Modulator circuits; Transmitter circuits

Abstract

A monolithic integrated circuit (IC), and method of manufacturing same, that includes all RF front end or transceiver elements for a portable communication device, including a power amplifier (PA), a matching, coupling and filtering network, and an antenna switch to couple the conditioned PA signal to an antenna. An output signal sensor senses at least a voltage amplitude of the signal switched by the antenna switch, and signals a PA control circuit to limit PA output power in response to excessive values of sensed output. Stacks of multiple FETs in series to operate as a switching device may be used for implementation of the RF front end, and the method and apparatus of such stacks are claimed as subcombinations. An iClass PA architecture is described that dissipatively terminates unwanted harmonics of the PA output signal. A preferred embodiment of the RF transceiver IC includes two distinct PA circuits, two distinct receive signal amplifier circuits, and a four-way antenna switch to selectably couple a single antenna connection to any one of the four circuits.

Claims

1. An integrated RF Power Amplifier (PA) circuit, comprising:

a) an input node to accept an input signal with respect to a reference voltage Vref, connected to a first gate G1 of a first MOSFET M1, wherein a source of MOSFET M1 is connected to Vref;

b) a plurality of additional MOSFETs M2 to Mn having associated and corresponding gates G2 to Gn, connected in series with the MOSFET M1 to form a transistor stack, wherein the MOSFET M1 comprises a bottom transistor of the transistor stack, and the MOSFET Mn comprises a top transistor of the transistor stack, wherein the transistor stack is configured to control conduction between the reference voltage Vref and an output drive node, and wherein the output drive node is connected to the drain of the top transistor Mn of the transistor stack;

c) a matching, coupling and filtering circuit connected to the output drive node, wherein the matching, coupling and filtering circuit is disposed between the output drive node and an external antenna; and

d) a corresponding predominantly capacitive element connected directly between each gate, G2 to Gn, and Vref;

wherein both RF and DC voltages are divided across the transistor stack, and wherein each MOSFET M2 to Mn has associated and corresponding bias resistors RB2 to RBn connected to their associated and corresponding gates of G2 to Gn, wherein the bias resistors RB2 to RBn are connected to associated and corresponding bias voltages VB2 to VBn, wherein the bias voltages VB2 to VBn may be individually selected to adjust the DC voltage divided across each MOSFET M2 to Mn, and wherein the divided DC voltage across each MOSFET M2 to Mn may be controlled by the bias voltages VB2 to VBn to be identical, or they may be controlled by the bias voltages to be any desired divided DC voltage.

2. The integrated RF PA of claim 1, wherein each MOSFET M2 to Mn has a corresponding and associated gate capacitor CG2 to CGn connected to the gate of each MOSFET M2 to Mn, and also connected to a ground reference, and wherein the RF voltage divided across each MOSFET M2 to Mn of the transistor stack is determined by values of the associated and corresponding gate capacitors CG2 to CGn.

3. The integrated RF PA of claim 2, wherein the DC and RF voltage divided across any one of the transistors M2 to Mn of the transistor stack is controlled by the associated and corresponding bias voltages and gate capacitors, respectively, and wherein the DC and RF voltages divided across any one of the individual MOSFETs M2 to Mn of the transistor stack are independently controlled.

4. The integrated RF PA of claim 2, wherein the DC and RF voltage divided across each of the MOSFET transistors M2 to Mn of the transistor stack are approximately equal.

5. The integrated RF PA of claim 2, wherein the DC and RF voltage divided across any one of the MOSFET transistors M2 to Mn of the transistor stack are set to be any desired value.

6. The integrated RF PA of claim 3, wherein the DC and RF voltage across any one of the plurality of MOSFETs M2 to Mn are independently controlled by setting the associated and corresponding bias voltage and gate capacitance values, respectively, to desired values.

7. The integrated RF PA of claim 1, wherein the MOSFETs comprise N-MOSFETs.

8. The integrated RF PA of claim 1, wherein the MOSFETs comprise P-MOSFETs.

9. The integrated RF PA of claim 1, wherein the MOSFETs M1 to Mn are fabricated in a silicon layer of a silicon-on-insulator (SOI) substrate.

10. The integrated RF PA of claim 9, wherein the MOSFETs M1 to Mn have associated and corresponding sources and drains, and wherein the sources and the drains extend through an entire thickness of the silicon layer and further down to an insulating layer of the SOI substrate.

11. The integrated RF PA of claim 1, wherein each MOSFET M1 to Mn of the transistor stack has an associated and corresponding drain-to-source voltage Vds, and wherein the Vds of each MOSFET of the transistor stack are approximately equal.

12. The integrated RF PA of claim 1, wherein each MOSFET M1 to Mn of the transistor stack has an associated and corresponding drain-to-source voltage Vds, and wherein the Vds of the MOSFETs of the transistor stack are unequal to each other.

13. The integrated RF PA of claim 1, wherein voltage is divided approximately equally across each MOSFET of the transistor stack.

14. The integrated RF PA of claim 1, wherein voltage is divided unequally across each MOSFET of the transistor stack.

15. The integrated RF PA of claim 1, wherein the MOSFETs M1 to Mn have associated and corresponding sources and drains, wherein the source of the bottom transistor M1 is connected to Vref, and wherein the MOSFETs M1 to Mn are connected in series by connecting a drain of a preceding transistor in the stack to a source of a next transistor in the transistor stack.

16. The integrated RF PA of claim 1, further comprising an output filter section connected in series with the matching, coupling and filtering circuit and disposed between the matching, coupling and filtering circuit and an RF switch, wherein the RF switch connects the output filter section to the external antenna when the RF switch is in an ON (conducting) state.

17. The integrated RF PA of claim 1, wherein the RF PA comprises a Class A, B, or C, AB, or F RF PA.

37. An RF front-end circuit, comprising:

a) an RF signal amplifier configured to receive a transmit signal having frequency content and phasing that is substantially suitable for transmitting, and to amplify such signal to establish an amplified transmit signal;

b) an RF power amplifier (PA) circuit according to claims 1 or 28, wherein the input node is connected to the input signal, and wherein the input signal is derived from the amplified transmit signal, and wherein the RF PA is configured to amplify the input signal to generate a power amplified transmit signal having a power amplifier output characteristic impedance, and including a regulator circuit configured to controllably constrain an amplitude of the power amplified transmit signal;

c) wherein the matching, coupling and filtering circuit is configured to condition the power amplified transmit signal by blocking DC components, changing the characteristic impedance of the signal, and rejecting unwanted frequencies, to establish an antenna-matched transmit signal;

d) an antenna switch configured to controllably connect the antenna-matched transmit signal to an antenna connection node, or to decouple the antenna connection node from the transmit signal and connected to the antenna connection node instead to a receive signal amplification path;

e) a transmit signal sensing circuit configured to generate a transmit power signal that reflects at least an amplitude of the transmit signal that is connected via the antenna switch; and

f) a control circuit configured to cause the regulator circuit to constrain the power amplified transmit signal in response to the transmit power signal so as to substantially prevent the amplitude of the transmit signal connected by the antenna switch from exceeding a predetermined limit.

38. Integrated RF front-end circuitry on a monolithic integrated circuit, comprising:

a) an RF signal amplifier configured to receive a transmit signal having frequency content and phasing that is substantially suitable for transmitting, and to amplify such signal to establish an amplified transmit signal;

b) an RF power amplifier (PA) circuit according to claims 1 or 28 , wherein the input node is connected to the input signal, wherein the input signal is derived from the amplified transmit signal, and wherein the RF PA is configured to amplify the input signal to generate a power amplified transmit signal having a power amplifier output characteristic impedance, and including a regulator circuit configured to controllably constrain an amplitude of the power amplified transmit signal;

c) wherein the matching, coupling and filtering network is configured to condition the power amplified transmit signal by blocking DC components, changing the characteristic impedance of the signal, and rejecting unwanted frequencies, to establish an antenna-matched transmit signal;

d) an antenna switch configured to controllably connect the antenna-matched transmit signal to an antenna connection node, or to decouple the antenna connection node from the transmit signal and connect the antenna connection node instead to a receive signal amplification path;

e) a transmit signal sensing circuit configured to generate a transmit power signal that reflects at least an amplitude of the transmit signal that is connected via the antenna switch; and

f) a control circuit configured to cause the regulator circuit to constrain the power amplified transmit signal in response to the transmit power signal so as to substantially prevent the amplitude of the transmit signal connected by the antenna switch from exceeding a predetermined limit.

18. A multiple-MOSFET stack circuit for controlling conduction between a drive output node Vdrive and a reference voltage node Vref under control of an input signal applied between an input signal node and Vref, the circuit comprising:

a) a series transistor stack of J MOSFETs M_N, N an integer between 1 and J and J an integer 3 or greater, each MOSFET M_N having a source S_N, a gate G_N and a drain D_N,

b) an input signal node connected to the gate G₁ of a signal-input MOSFET M₁ of the MOSFET stack;

c) for 0<

N <

J, a series coupling between each drain D_N and the source S_(N+1) of a next higher MOSFET M_(N+1) of the MOSFET transistor stack;

d) for 1<

N ≦

J, a gate coupling element that is predominately capacitive connected directly between each gate G_N and Vref, wherein, for 1<

N ≦

J, each MOSFET M_N is biased to avoid exceeding breakdown characteristics of the FET M_N; and

where each gate G_N is provided with a suitable bias voltage, and wherein the bias voltage is decoupled to Vref;

e) a source coupling for the FET stack between S₁ and Vref; and

f) a drain coupling for the FET stack between D_J and Vdrive;

wherein both RF and DC voltages are divided across the transistor stack, and wherein each MOSFET M₂ to M_N has associated and corresponding bias resistors RB₂ to RB_N connected to their associated and corresponding gates of G₂ to G_N, wherein the bias resistors RB₂ to RB_N are connected to associated and corresponding bias voltages VB₂ to VB_N, wherein the bias voltages VB₂ to VB_N may be individually selected to adjust the DC voltage divided across each corresponding and associated MOSFET M₂ to M_N, and wherein the divided DC voltage across each MOSFET M₂ to M_N may be controlled by the bias voltages VB₂ to VB_N to be identical, or they may be controlled by the bias voltages to be any desired divided DC voltage.

19. The circuit of claim 18, wherein each MOSFET M₂ to M_N has a corresponding and associated gate capacitor CG₂ to CG_N connected to the gate of each MOSFET M₂ to M_N, and also connected to a ground reference, and wherein the RF voltage divided across each MOSFET M₂ to M_N of the MOSFET transistor stack is determined by values of the associated and corresponding gate capacitors CG₂ to CG_N.

20. The circuit of claim 19, wherein the DC and RF voltage divided across any one of the transistors M₂ to M_N of the transistor stack is controlled by the associated and corresponding bias voltages and gate capacitors, respectively, and wherein the DC and RF voltages divided across any one of the individual MOSFETs M₂ to M_N of the transistor stack are independently controlled.

21. The circuit of claim 19, wherein the DC and RF voltage divided across each of the transistors M₂ to M_N of the transistor stack are approximately equal.

22. The circuit of claim 19, wherein the DC and RF voltage divided across any one of the transistors M₂ to M_N of the transistor stack are set to be any desired value.

23. The circuit of claim 20, wherein the DC and RF voltage across any one of the plurality of MOSFETs M₂ to M_N are independently controlled by setting the associated and corresponding bias voltage and gate capacitance values, respectively, to desired values.

24. The integrated circuit of claim 18, further comprising an integrated RF Power Amplifier (PA) circuit, the integrated RF PA circuit comprising:

i)an input node that is the input signal node of claim 18; and

ii) a matching, coupling and filtering circuit connected to the drive output node.

25. A Class A, B, C, AB, or F RF PA comprising a circuit according to claim 18, wherein the multiple-MOSFET stack is configured as a primary amplifying device of the Class A, B, or C, AB, or F RF PA.

26. A quad mixer comprising a circuit according to claim 18.

27. An RF power management circuit comprising a circuit according to Claim 18.

28. An integrated RF Power Amplifier (PA) circuit, comprising:

a) an input node to accept an input signal with respect to a reference voltage Vref, connected to a gate G1 of a first insulated-gate MOSFET M1;

b) a plurality of additional insulated-gate MOSFETs M2 to Mn connected in series with M1 to form a transistor stack wherein the plurality of MOSFETs M2 to Mn have associated and corresponding gates G2 to Gn, wherein the MOSFET M1 comprises a bottom transistor of the transistor stack, and the MOSFET Mn comprises a top transistor of the transistor stack, and wherein the transistor stack is configured to control conduction between the reference voltage and an output drive node, and wherein the output drive node is connected to a drain of the top transistor Mn of the transistor stack;

c) a matching, coupling and filtering circuit connected to the output drive node, wherein the matching, coupling and filtering circuit is disposed between the output drive node and an external antenna; and

d) an output power control input node connected to a power controlling insulated-gate MOSFET that is connected in series connection with M1.

29. The integrated RF PA of claim 28, wherein the power controlling MOSFET is disposed between the reference voltage and a power supply voltage external to the RF PA.

30. The integrated RF PA of claim 28, wherein the power controlling FET is one of the FETs M2 to Mn.

31. The integrated RF PA of claim 28, wherein both RF and DC voltages are divided across the transistor stack, and wherein each MOSFET M2 to Mn has associated and corresponding bias resistors RB2 to RBn connected to their associated and corresponding gates of G2 to Gn, wherein the bias resistors RB2 to RBn are connected to associated and corresponding bias voltages VB2 to VBn, wherein the bias voltages VB2 to VBn may be individually selected to adjust the DC voltage divided across each MOSFET M2 to Mn, and wherein the divided DC voltage across each MOSFET M2 to Mn may be controlled by the bias voltages VB2 to VBn to be identical, or they may be controlled by the bias voltages to be any desired divided DC voltage.

32. The integrated RF PA of claim 28, wherein each MOSFET M2 to Mn has a corresponding and associated gate capacitor CG2 to CGn connected to the gate of each MOSFET M2 to Mn, and also connected to a ground reference, and wherein the RF voltage divided across each MOSFET M2 to Mn of the transistor stack is determined by values of their associated and corresponding gate capacitors CG2 to CGn.

33. The integrated RF PA of claim 32, wherein the DC and RF voltage divided across any one of the transistors M2 to Mn of the transistor stack is controlled by the associated and corresponding bias voltages and gate capacitors, respectively, and wherein the DC and RF voltages divided across any one of the individual MOSFETs M2 to Mn of the transistor stack are independently controlled.

34. The integrated RF PA of claim 32, wherein the DC and RF voltage divided across each of the MOSFET transistors M2 to Mn of the transistor stack are approximately equal.

35. The integrated RF PA of claim 32, wherein the DC and RF voltage divided across each one of the transistors M2 to Mn of the transistor stack are set to be any desired value.

36. The integrated RF PA of claim 33, wherein the DC and RF voltage divided across any one of the plurality of MOSFETs M2 to Mn are independently controlled by setting the associated and corresponding bias voltage and gate capacitance values, respectively, to desired values.