Virtualized communication sockets for multi-flow access to message channel infrastructure within CPU

• US 9,697,059 B2
• Filed: 05/26/2015
• Issued: 07/04/2017
• Est. Priority Date: 10/09/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Sistla, Krishnakanth V., Borkowski, Daniel G.
• Primary Examiner(s): DAO, TUAN C.
• Application Number:
  US14/722,049
• Publication Number:
  US 20150254118A1
• Time in Patent Office: 770 Days
• Field of Search: None
• CPC Class Codes: G06F 13/4059 where the synchronisation uses buffers, e.g. for speed matching between buses
• CPC Class Codes: G06F 9/544 Buffers; Shared memory; Pipes
• CPC Class Codes: G06F 9/545 where tasks reside in different layers, e.g. user- and kernel-space
• CPC Class Codes: G06F 9/546 Message passing systems or structures, e.g. queues

Abstract

A message channel optimization method and system enables multi-flow access to the message channel infrastructure within a CPU of a processor-based system. A user (pcode) employs a virtual channel to submit message channel transactions, with the message channel driver processing the transaction “behind the scenes”. The message channel driver thus allows the user to continue processing without having to block other transactions from being processed. Each transaction will be processed, either immediately or at some future time, by the message channel driver. The message channel optimization method and system are useful for tasks involving message channel transactions as well as non-message channel transactions.

Claims

1. A processor-based system comprising:

a central processing unit (CPU), a first endpoint, and a second endpoint;

a message channel to enable communication between the first endpoint and the second endpoint;

a message channel driver to interface between one or more virtual message channels of the first endpoint and the message channel; and

a plurality of users, each user to represent a portion of the portable machine code (pcode) flow through the processor-based system, a virtual channel identifier (VCID) to be assigned to each user that uses the message channel, wherein each pcode flow with a VCID is capable of registering a callback address;

wherein each user with a VCID can submit one message channel transaction for processing;

wherein a user of the plurality of users;

issues a first application programming interface (API) function to determine whether a virtual message channel of the one or more virtual message channels is available, wherein a virtual channel identifier (VCID) associated with the user is provided as input to the first API function;

issues a second API function in response to the virtual message channel becoming available; and

registers a callback address to be used by the message channel driver;

wherein the message channel driver registers an event to cause a kernel in the CPU to run a callback function to the callback address.

2. The processor-based system of claim 1, wherein the second API function either returns contents of the virtual message channel specified by the VCID or sends a message on the message channel using the virtual message channel specified by the VCID.

3. The processor-based system of claim 1, further comprising:

helper functions;

wherein the API functions and helper functions assist with message channel transactions.

4. The processor-based system of claim 3, wherein each user interfaces with the message channel driver via the API functions and the message channel driver interfaces with the CPU.

5. The processor-based system of claim 3, further comprising:

a third API function to send a power management request message on the message channel using the virtual message channel specified by the VCID;

wherein the API functions are used by both the users and the message channel driver.

6. The processor-based system of claim 3, the helper functions further comprising:

a first helper function to enable the message channel driver to send data to the message channel; and

a second helper function to enable the message channel driver to poll the physical message channel for completion of an operation;

wherein the first and second helper functions are used by the message channel driver and not by the user.

7. The processor-based system of claim 1, further comprising:

a queue available to the message channel driver, the queue to store transactions that are waiting to be processed.

8. The processor-based system of claim 7, wherein the queue is a first-in-first-out queue.

9. The processor-based system of claim 1, the message channel driver to:

execute a data preparation portion of a first task, the first task comprising the data preparation, issuance of a message channel transaction, and results processing;

send a function to the CPU, wherein the function causes the message channel transaction to be queued by the message channel driver; and

execute a second task, the second task comprising no message channel transaction, wherein the second task is executed irrespective of whether the message channel transaction of the first task is completed;

wherein the message channel driver, upon receiving a hardware event, transfers the message channel transaction from one of the one or more virtual message channels to the message channel where the message channel transaction is carried by the message channel to the second endpoint.

10. The processor-based system of claim 1, further comprising:

a second CPU; and

a quick path interconnect (QPI) bus coupled between the CPU and the second CPU.