Power loss protection integrated circuit

• US 9,705,402 B1
• Filed: 07/01/2016
• Issued: 07/11/2017
• Est. Priority Date: 06/25/2016
• Status: Active Grant

• Current Assignee: Active-Semi, Inc. (Qorvo, Inc.)
• Original Assignee: Active-Semi, Inc. (Qorvo, Inc.)
• Inventors: Smith, Brett E., Watanabe, Hiroshi, Carpenter, Jr., John H.
• Primary Examiner(s): Nguyen, Matthew
• Assistant Examiner(s): Jamali, Ishrat
• Application Number:
  US15/201,265
• Time in Patent Office: 375 Days
• CPC Class Codes: G01R 19/2513 Arrangements for monitoring electric power systems, e.g. power lines or loads; Logging
• CPC Class Codes: G01R 27/2605 Measuring capacitance capacitive sensors G01D5/24
• CPC Class Codes: G01R 31/3835 involving only voltage measurements
• CPC Class Codes: G01R 31/392 Determining battery ageing or deterioration, e.g. state of health
• CPC Class Codes: G01R 31/64 Testing of capacitors
• CPC Class Codes: G05B 11/28 using pulse-height modulation; using pulse-width modulation
• CPC Class Codes: G05B 15/02 electric
• CPC Class Codes: G05F 1/66 Regulating electric power
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs
• CPC Class Codes: G06F 11/3013 where the computing system is an embedded system, i.e. a combination of hardware and software dedicated to perform a certain function in mobile devices, printers, automotive or aircraft systems testing or monitoring of control systems or parts thereof G05B23/02
• CPC Class Codes: G06F 11/3062 where the monitored property is the power consumption power management in a computing system G06F1/3203
• CPC Class Codes: G06F 2201/81 Threshold
• CPC Class Codes: H01H 85/0241 Structural association of a fuse and another component or apparatus switches with built-in fuses H01H9/10, spark-gap arresters H01H85/44, transformers and inductances H01F27/402, capacitors H01G2/14, lamps H01K1/66, semiconductors H01L23/5256 or H01L23/62
• CPC Class Codes: H02H 3/08 responsive to excess current responsive to abnormal temperature caused by excess current H02H5/04
• CPC Class Codes: H02J 9/061 for DC powered loads
• CPC Class Codes: H02M 1/0009 Devices or circuits for detecting current in a converter
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 1/32 Means for protecting converters other than automatic disconnection
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators
• CPC Class Codes: H02M 3/158 : including plural semiconductor devices as final control devices for a single load
• CPC Class Codes: H02M 3/1582 : Buck-boost converters H02M3/1584 takes precedence
• CPC Class Codes: H02M 3/1588 : comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: H03M 1/122 : Shared using a single converter or a part thereof for multiple channels, e.g. a residue amplifier for multiple stages
• CPC Class Codes: H03M 1/765 : using a single level of switches which are controlled by unary decoded digital signals

Abstract

A power loss protection integrated circuit includes a current switch circuit (eFuse), a VIN terminal, a VOUT terminal, a buck/boost controller, and a storage capacitor terminal STR. The controller is adapted to work: 1) as a boost to take a low voltage from the VOUT terminal and to output a larger charging voltage onto the STR terminal, or 2) as a buck to take a higher voltage from the STR terminal and to buck it down to a lower voltage required on the VOUT terminal. The current switch circuit outputs a digital undervoltage signal (UV) and a digital high current signal (HC). These signals are communicated on-chip to the controller. Asserting UV causes the converter to begin operating in the buck mode. Asserting HC prevents the converter from operating in the boost mode.

Claims

1. An integrated circuit comprising:

an input voltage terminal (VIN);

an output voltage terminal (VOUT);

a current switch circuit that can receive a current of up to a maximum input current from the input voltage terminal VIN and can conduct that current to the output voltage terminal VOUT, wherein the current switch circuit outputs a digital undervoltage signal and a digital high current signal;

a storage capacitor terminal (STR);

a switch terminal (SW);

a feedback terminal (FB); and

a buck/boost controller coupled to the switch terminal SW and to the feedback terminal FB, wherein the buck/boost controller is adapted to operate in a buck mode and in a boost mode, wherein in the buck mode the buck/boost controller drives the switch terminal SW so that the buck/boost controller in combination with an external inductor can operate as a buck converter, wherein in the buck mode the buck converter receives a relatively high input supply voltage from the storage capacitor terminal STR, wherein in the boost mode the buck/boost controller drives the switch terminal SW so that the buck/boost controller in combination with the external inductor operates as a boost converter and outputs a relatively high voltage onto the storage capacitor terminal STR, wherein the buck/boost controller is made to begin operating in the buck mode if the digital undervoltage signal is asserted, wherein the buck/boost controller is prevented from operating in the boost mode if the digital high current signal is asserted, and wherein the integrated circuit includes no processor that fetches, decodes and executes any instructions.

2. The integrated circuit of claim 1, further comprising:

a digital state machine that receives the digital undervoltage signal from the current switch circuit and that receives the digital high current signal from the current switch circuit, wherein the digital state machine supplies a boost disable digital control signal to the buck/boost controller, wherein the digital state machine supplies a buck on digital control signal to the buck/boost controller, and wherein the maximum input current is at least two amperes.

3. The integrated circuit of claim 1, wherein the current switch circuit is open when the digital undervoltage signal is asserted, and wherein the opening of the current switch circuit prevents current from flowing from the output voltage terminal VOUT through the current switch circuit and to the input voltage terminal VIN.

4. The integrated circuit of claim 1, wherein the current switch circuit comprises a field effect transistor switch coupled between the input voltage terminal VIN and the output voltage terminal VOUT, wherein in a first current range of current flowing through the current switch circuit the field effect transistor switch is fully on, wherein in a second current range of current flowing through the current switch the resistance of the field effect transistor switch is linearly regulated to limit current flow through the current switch circuit, wherein in a third current range the field effect transistor switch is duty cycled on and off, and wherein the current switch circuit asserts the digital high current signal when the current switch circuit is operating in the second current range and in the third current range.

5. The integrated circuit of claim 1, wherein a single comparator of the current switch circuit generates the digital undervoltage signal, and wherein the digital undervoltage signal both:

1) causes the current switch circuit to open such that there is no current flow between the input voltage terminal VIN and the output voltage terminal VOUT through the current switch circuit, and

     2) causes the buck/boost controller to begin operating in the buck mode.

6. The integrated circuit of claim 1, further comprising:

a sequential digital logic element, wherein the current switch circuit is forced to be open if the sequential digital logic element is set, wherein the forcing of the current switch circuit to be open prevents current from flowing from the output voltage terminal VOUT through the current switch circuit and to the input voltage terminal VIN, and wherein the forcing of the current switch circuit to be open also prevents current from flowing from the input voltage terminal VIN through the current switch circuit and to the output voltage terminal VOUT; and

a serial bus interface circuit, wherein the serial bus interface circuit is operable to set the sequential digital logic element.

7. The integrated circuit of claim 1, further comprising:

a sequential digital logic element, wherein if the sequential digital logic element is set then the buck/boost controller is forced to operate in one of the buck mode and the boost mode; and

a serial bus interface circuit, wherein the serial bus interface circuit is operable to set the sequential digital logic element.

8. The integrated circuit of claim 1, wherein the buck/boost controller is not coupled to the external inductor but rather is adapted to be coupled to the external inductor, and wherein the buck/boost controller is not operating as part of any buck converter or as part of any boost converter but rather is adapted to operate as part of a buck converter and part of a boost converter.

9. The integrated circuit of claim 1, wherein the current switch circuit also outputs a digital overvoltage signal, wherein the digital overvoltage signal indicates whether a voltage on the input voltage terminal VIN is greater than a programmable voltage, wherein the current switch circuit comprises a register, and wherein a multi-bit digital value stored in the register determines the programmable voltage.

10. An integrated circuit comprising:

an input voltage terminal (VIN);

an output voltage terminal (VOUT);

an eFuse means for receiving a current from the input voltage terminal VIN and for conducting that current to the output voltage terminal VOUT, wherein the eFuse means is for decoupling the input voltage terminal VIN from the output voltage terminal VOUT in a fault condition such that in the fault condition there is no current flow between the input voltage terminal VIN and the output voltage terminal VOUT, and wherein the eFuse means is also for outputting a digital undervoltage signal and a digital high current signal;

a storage capacitor terminal (STR);

a switch terminal (SW);

a feedback terminal (FB); and

a buck/boost controller coupled to the switch terminal SW and to the feedback terminal FB, wherein the buck/boost controller is adapted to operate in a buck mode and in a boost mode, wherein in the buck mode the buck/boost controller drives the switch terminal SW so that the buck/boost controller in combination with an external inductor can operate as a buck converter, wherein in the buck mode the buck converter receives a relatively high input supply voltage from the storage capacitor terminal STR, wherein in the boost mode the buck/boost controller drives the switch terminal SW so that the buck/boost controller in combination with the external inductor operates as a boost converter and outputs a relatively high voltage onto the storage capacitor terminal STR, wherein the buck/boost controller is made to begin operating in the buck mode if the digital undervoltage signal is asserted, wherein the buck/boost controller is prevented from operating in the boost mode if the digital high current signal is asserted, and wherein the integrated circuit includes no processor that fetches, decodes and executes any instructions.

11. The integrated circuit of claim 10, further comprising:

a current set terminal (ISET), wherein the eFuse means asserts the digital high current signal if a through-current flowing through eFuse means exceeds a predetermined current, and wherein the eFuse means is adapted to set the predetermined current as a function of a resistance of an external resistor coupled to the current set terminal ISET.

12. The integrated circuit of claim 10, wherein the eFuse means comprises an override bit, and wherein if the override bit is set then the eFuse is forced open such that the input voltage terminal VIN is decoupled from the output voltage terminal VOUT.

13. The integrated circuit of claim 12, further comprising:

a serial bus interface, wherein the override bit can be written via the serial bus interface.

14. The integrated circuit of claim 12, further comprising:

an enable terminal (EN); and

a comparator having a first input lead coupled to the enable terminal EN and having a second input coupled to receive a reference voltage, wherein the comparator has an output lead from which the digital undervoltage signal is output.

15. The integrated circuit of claim 10, wherein the digital undervoltage signal is asserted by the eFuse means if a voltage in the input voltage terminal VIN is smaller than a predetermined voltage, and wherein the predetermined voltage is user-settable by selection of external resistances coupled to a terminal of the integrated circuit.

16. The integrated circuit of claim 10, wherein the buck/boost controller comprises an override bit, and wherein if the override bit is set then the buck/boost controller is forced to turn on and begin operating in a boost mode.

17. The integrated circuit of claim 16, further comprising:

a serial bus interface, wherein the override bit can be written via the serial bus interface.

18. The integrated circuit of claim 10, wherein the buck/boost controller comprises an override bit, and wherein if the override bit is set then the buck/boost controller is forced to turn on and begin operating in a buck mode.

19. The integrated circuit of claim 18, further comprising:

a serial bus interface, wherein the override bit can be written via the serial bus interface.

20. An integrated circuit comprising:

an input voltage terminal (VIN);

an output voltage terminal (VOUT);

an eFuse means for receiving a current from the input voltage terminal VIN and for conducting that current to the output voltage terminal VOUT, wherein the eFuse means is for decoupling the input voltage terminal VIN from the output voltage terminal VOUT in a fault condition such that in the fault condition there is no current flow between the input voltage terminal VIN and the output voltage terminal VOUT, and wherein the eFuse means is also for outputting a digital undervoltage signal;

a storage capacitor terminal (STR);

a switch terminal (SW);

a feedback terminal (FB); and

a buck controller coupled to the switch terminal SW and to the feedback terminal FB, wherein the buck controller is adapted to operate in combination with components external to the integrated circuit as part of a buck converter, wherein the buck converter is adapted to receive a relatively high voltage from the storage capacitor terminal STR and to buck the relatively high voltage down to a relatively low voltage that is supplied onto the output voltage terminal VOUT, wherein asserting of the digital undervoltage signal causes the buck converter to begin operating and to begin supplying the relatively low voltage onto the output voltage terminal VOUT, and wherein the integrated circuit includes no processor that fetches, decodes and executes any instructions.