Reducing latency for pointer chasing loads

• US 9,710,268 B2
• Filed: 04/29/2014
• Issued: 07/18/2017
• Est. Priority Date: 04/29/2014
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Kanapathipillai, Pradeep, Gupta, Sandeep, Meier, Stephan G.
• Primary Examiner(s): Lindlof, John
• Application Number:
  US14/264,789
• Publication Number:
  US 20150309792A1
• Time in Patent Office: 1,176 Days
• Field of Search: None
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/3826 Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00

Abstract

Systems, methods, and apparatuses for reducing the load to load/store address latency in an out-of-order processor. When a producer load is detected in the processor pipeline, the processor predicts whether the producer load is going to hit in the store queue. If the producer load is predicted not to hit in the store queue, then a dependent load or store can be issued early. The result data of the producer load is then bypassed forward from the data cache directly to the address generation unit. This result data is then used to generate an address for the dependent load or store, reducing the latency of the dependent load or store by one clock cycle.

Claims

1. A processor comprising:

a load-store unit (LSU);

a store queue; and

a load-store dependency predictor configured to generate a prediction as to whether a load operation is going to hit in the store queue;

wherein the processor is configured to;

determine that a younger memory operation is dependent on an older load operation;

generate, by the load-store dependency predictor, a prediction as to whether the older load operation will hit in the store queue;

in response to the prediction indicating that the older load operation is predicted to hit in the store queue, issue the younger memory operation N clock cycles subsequent to the older load operation, wherein N is a positive integer; and

in response to the prediction indicating that the older load operation is predicted to miss in the store queue, issue the younger memory operation M clock cycles subsequent to the older load operation, wherein M is a positive integer less than N.

2. The processor as recited in claim 1, wherein the LSU is configured to forward result data from a data cache to an address generation unit for the younger memory operation responsive to determining that the prediction indicates the older load operation is predicted to miss in the store queue.

3. The processor as recited in claim 1, wherein the load-store dependency predictor comprises a table with entries configured to store information for loads that have been trained.

4. The processor as recited in claim 1, wherein the load-store dependency predictor is further configured to:

predict if the older load operation has a word-boundary aligned address; and

predict if result data of the older load operation requires a sign extension.

5. The processor as recited in claim 2, wherein the processor is further configured to utilize the result data to compute an address for the younger memory operation.

6. The processor as recited in claim 1, wherein the younger memory operation is a store operation.

7. The processor as recited in claim 1, wherein the processor is further configured to issue the younger memory operation M clock cycles subsequent to the older load operation in further response to determining:

result data corresponding to the older load operation is word boundary aligned; and

the result data does not require a sign extension.

8. A method comprising:

determining that a younger memory operation is dependent on an older load operation;

generating, a load-store dependency predictor, a prediction as to whether the older load operation will hit in a store queue of a load-store unit;

in response to the prediction indicating that the older load operation is predicted to hit in the store queue, issuing the younger memory operation N clock cycles subsequent to the older load operation, wherein N is a positive integer; and

in response to the prediction indicating that the older load operation is predicted to miss in the store queue, issuing the younger memory operation M clock cycles subsequent to the older load operation, wherein M is a positive integer less than N.

9. The method as recited in claim 8, wherein M is equal to N−

1.

10. The method as recited in claim 8, further comprising forwarding result data from a data cache for the younger memory operation responsive to determining that the prediction indicates the older load operation is predicted to miss in the store queue.

11. The method as recited in claim 9, further comprising issuing the younger memory operation M clock cycles after the older load operation in further response to determining that result data of the older load operation is word boundary aligned.

12. The method as recited in claim 9, further comprising issuing the younger memory operation M clock cycles after the older load operation in further response to determining that result data of the older load operation does not require a sign extension.

13. The method as recited in claim 8, wherein said determining is performed prior to issuing the younger memory operation.

14. A system comprising:

a processor; and

a memory;

a load-store dependency predictor configured to generate a prediction as to whether a load operation is going to hit in the store queue;

wherein the processor is configured to;

determine that a younger memory operation is dependent on an older load operation;

generate, by the load-store dependency predictor, a prediction as to whether the older load operation will hit in the store queue;

in response to the prediction indicating that the older load operation is predicted to hit in the store queue, issue the younger memory operation N clock cycles subsequent to the older load operation, wherein N is a positive integer; and

in response to the prediction indicating that the older load operation is predicted to miss in the store queue, issue the younger memory operation M clock cycles subsequent to the older load operation, wherein M is a positive integer less than N.

15. The system as recited in claim 14, wherein the processor is further configured to forward result data from a data cache directly to an address generation unit for the younger memory operation.

16. The system as recited in claim 14, wherein the processor is configured to train the load-store dependency predictor responsive to a mispredict of a given older load operation.

17. The system as recited in claim 14, wherein the processor is configured to flush a corresponding younger memory operation responsive to detecting a mispredict of the older load operation.

18. The system as recited in claim 15, wherein the address generation unit is configured to utilize the result data to compute an address for the younger memory operation.