Apparatuses and methods for providing set and reset voltages at the same time

• US 9,711,218 B2
• Filed: 02/13/2017
• Issued: 07/18/2017
• Est. Priority Date: 04/12/2012
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Marotta, Giulio-Giuseppe, Tiburzi, Marco-Domenico
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US15/431,364
• Publication Number:
  US 20170154676A1
• Time in Patent Office: 155 Days
• Field of Search: None
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0026 Bit-line or column circuits
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 13/0038 Power supply circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0061 Timing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/0097 Erasing, e.g. resetting, circuits or methods
• CPC Class Codes: G11C 2013/0083 Write to perform initialising, forming process, electro forming or conditioning
• CPC Class Codes: G11C 2013/0085 Write a page or sector of information simultaneously, e.g. a complete row or word line
• CPC Class Codes: G11C 2013/0088 Write with the simultaneous writing of a plurality of cells
• CPC Class Codes: G11C 2213/79 Array wherein the access device being a transistor
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

Apparatuses and methods are described, such as those involving driver circuits that are configured to provide reset and set voltages to different variable state material memory cells in an array at the same time. Additional apparatuses, and methods are described.

Claims

1. A memory device, comprising:

an array of memory cells arranged in rows and columns, each of the cells including;

a variable state material region;

an access transistor coupled the variable state material region; and

a driver coupled to the array of memory cells to provide three different voltages to different memory cells in the array at the same time, the three different voltages including set and reset voltages to different columns in the array at the same time.

2. The memory device of claim 1, wherein the variable state material region includes a resistance switching material.

3. The memory device of claim 2, wherein the variable state material region includes a unipolar variable state material.

4. The memory device of claim 2, wherein the variable state material region includes a bipolar variable state material.

5. The memory device of claim 1, wherein the driver is a column driver.

6. The memory device of claim 1, wherein the set voltage is configured to operate at approximately 4 volts operate at approximately 4 volts.

7. The memory device of claim 1, wherein the reset voltage is configured to operate at approximately 2 volts operate at approximately 2 volts.

8. The memory device of claim 1, wherein the access transistor includes an N channel access transistor.

9. The memory device of claim 1, wherein the access transistor includes a P channel access transistor.

10. A memory device, comprising:

an array of memory cells arranged in rows and columns, each of the cells including;

a variable state material region;

an access transistor coupled the variable state material region; and

a driver coupled to the array of memory cells to provide set, reset, and inhibit voltages to different columns in the array at the same time.

11. The memory device of claim 10, wherein the variable state material region includes a resistance switching material.

12. The memory device of claim 11, wherein the variable state material region includes a unipolar variable state material.

13. The memory device of claim 11, wherein the variable state material region includes a bipolar variable state material.

14. The memory device of claim 10, wherein the set voltage is configured to operate at approximately 4 volts.

15. The memory device of claim 14, wherein the reset voltage is configured to operate at approximately 2 volts.

16. The memory device of claim 15, wherein the inhibit voltage is configured to operate at approximately 3 volts.