Semiconductor device and manufacturing method thereof

• US 9,711,651 B2
• Filed: 09/10/2015
• Issued: 07/18/2017
• Est. Priority Date: 12/26/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Koyama, Jun, Sakata, Junichiro
• Primary Examiner(s): Slutsker, Julia
• Application Number:
  US14/849,928
• Publication Number:
  US 20160005876A1
• Time in Patent Office: 677 Days
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device which includes a thin film transistor having an oxide semiconductor layer and excellent electrical characteristics is provided. Further, a method for manufacturing a semiconductor device in which plural kinds of thin film transistors of different structures are formed over one substrate to form plural kinds of circuits and in which the number of steps is not greatly increased is provided. After a metal thin film is formed over an insulating surface, an oxide semiconductor layer is formed thereover. Then, oxidation treatment such as heat treatment is performed to oxidize the metal thin film partly or entirely. Further, structures of thin film transistors are different between a circuit in which emphasis is placed on the speed of operation, such as a logic circuit, and a matrix circuit.

Claims

1. A semiconductor device comprising an inverter circuit and

a pixel, the inverter circuit comprising:

a first transistor; and

a second transistor,

wherein a source of the first transistor is electrically connected to a drain of the second transistor;

wherein a gate of the first transistor is electrically connected to the source of the first transistor,

wherein a channel formation region of at least one of the first transistor and the second transistor comprises a first oxide semiconductor layer and a second oxide semiconductor layer, the second oxide semiconductor layer comprising indium and zinc,

wherein the second oxide semiconductor layer is provided on the first oxide semiconductor layer, and

wherein the first oxide semiconductor layer has a lower resistivity than the second oxide semiconductor layer, and

the pixel comprising a third transistor,

wherein a channel formation region of the third transistor is formed of a single layer of a third oxide semiconductor layer.

2. The semiconductor device according to claim 1 wherein each of the first transistor and the second transistor is a bottom-gate n-channel transistor.

3. The semiconductor device according to claim 1 wherein each of the first transistor and the second transistor comprises a source electrode and a drain electrode formed over the second oxide semiconductor layer.

4. The semiconductor device according to claim 1 wherein the first transistor is a depletion transistor and the second transistor is an enhancement transistor.

5. The semiconductor device according to claim 1 wherein the second oxide semiconductor layer further comprises gallium.

6. A semiconductor device comprising an inverter circuit and a pixel,

the inverter circuit comprising:

a first transistor; and

a second transistor,

wherein a source of the first transistor is electrically connected to a drain of the second transistor;

wherein a gate of the first transistor is electrically connected to a drain of the first transistor,

wherein a channel formation region of at least one of the first transistor and the second transistor comprises a first oxide semiconductor layer and a second oxide semiconductor layer, the second oxide semiconductor layer comprising indium and zinc,

wherein the second oxide semiconductor layer is provided on the first oxide semiconductor layer, and

wherein the first oxide semiconductor layer has a lower resistivity than the second oxide semiconductor layer, and

the pixel comprising a third transistor,

wherein a channel formation region of the third transistor is formed of a single layer of a third oxide semiconductor layer.

7. The semiconductor device according to claim 6 wherein each of the first transistor and the second transistor is a bottom-gate n-channel transistor.

8. The semiconductor device according to claim 6 wherein each of the first transistor and the second transistor comprises a source electrode and a drain electrode formed over the second oxide semiconductor layer.

9. The semiconductor device according to claim 6 wherein each of the first transistor and the second transistor is an enhancement transistor.

10. The semiconductor device according to claim 6 wherein the second oxide semiconductor layer further comprises gallium.