Active rectifier and circuit for compensating for reverse current leakage using time delay scheme for zero reverse leakage current

• US 9,712,077 B2
• Filed: 07/09/2014
• Issued: 07/18/2017
• Est. Priority Date: 11/22/2013
• Status: Active Grant

• Current Assignee: Industry-University Cooperation Foundation Hanyang University, Samsung Electronics Co. Ltd.
• Original Assignee: Industry-University Cooperation Foundation Hanyang University, Samsung Electronics Co. Ltd.
• Inventors: Kim, Dong Zo, Kwon, Sang Wook, Kim, Ki Young, Kim, Bong Chul, Moon, Young Jin, Park, Jae Hyun, Yoo, Chang Sik, Lee, Byoung Hee
• Primary Examiner(s): Berhane, Adolf
• Assistant Examiner(s): Quddus, Nusrat
• Application Number:
  US14/326,829
• Publication Number:
  US 20150146466A1
• Time in Patent Office: 1,105 Days
• Field of Search: 363 52- 53, 363123, 363125-127
• CPC Class Codes: H02M 7/219 in a bridge configuration
• CPC Class Codes: H02M 7/2195 the switches being synchronously commutated at the same frequency of the AC input voltage
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A method of compensating for reverse current leakage in an active rectifier may include advancing an output of a comparator by a predetermined period of time by applying a predetermined offset voltage to a reference voltage input to the comparator, and activating a switch based on the output of the comparator. The method may also include deactivating the switch when a predetermined time delay elapses from a point in time at which the switch was activated.

Claims

1. A circuit for compensating for reverse current leakage in an active rectifier, the circuit comprising:

a switch configured to control a current flow in the active rectifier and interrupt the current flow in response to the switch being deactivated; and

a reverse current leakage compensator configured to deactivate the switch in response to a predetermined time delay elapsing from a point in time at which the switch is activated,

wherein the reverse current leakage compensator is further configured to detect a rising edge and output a control signal based on the rising edge and a signal delayed from the rising edge.

2. The circuit of claim 1, wherein the reverse current leakage compensator comprises:

a rising edge detector configured to detect the rising edge;

a delay unit configured to output the signal delayed from the rising edge by the predetermined time delay; and

a set-reset (SR) latch configured to output the control signal in response to the rising edge and the signal delayed from the rising edge.

3. The circuit of claim 1, wherein the reverse current leakage compensator comprises:

a comparator configured to output a comparison result obtained by comparing an input signal to a reference voltage;

an inverter configured to invert the output of the comparator;

a capacitor configured to delay an output of the inverter by the predetermined time delay; and

a negated AND (NAND) gate configured to output a control signal in response to the output of the inverter delayed by the capacitor and the output of the comparator.

4. The circuit of claim 1, wherein the reverse current leakage compensator comprises:

a comparator configured to adjust a reference voltage by a predetermined offset voltage to advance an output of the comparator by a predetermined period of time;

wherein the switch is further configured to be activated based on an output of the comparator.

5. The circuit of claim 4, wherein the predetermined offset voltage is applied by a resistor divider.

6. The circuit of claim 4, wherein the predetermined offset voltage is applied by a diode.

7. An active rectifier comprising:

a first loop configured to enable a current to flow in the first loop, the first loop being activated in an interval in which an input signal has a positive phase; and

a second loop configured to enable a current to flow in the second loop, the second loop being activated in an interval in which the input signal has a negative phase;

wherein each of the first loop and the second loop comprises a switch and a controller configured to generate a control signal to deactivate the switch in response to a predetermined time delay elapsing from a point in time at which the switch is activated,

wherein the controller is further configured to detect a rising edge of the input signal and output a control signal based on the rising edge and a signal delayed from the rising edge.

8. The active rectifier of claim 7, wherein the controller comprises:

a rising edge detector configured to detect the rising edge of the input signal;

a delay unit configured to output the signal delayed from the rising edge by the predetermined time delay; and

a set-reset (SR) latch configured to output the control signal in response to the rising edge and the signal delayed from the rising edge.

9. The active rectifier of claim 7, wherein the controller comprises:

a comparator configured to output a comparison result obtained by comparing the input signal to a reference voltage;

an inverter configured to invert the output of the comparator;

a capacitor configured to delay an output of the inverter by the predetermined time delay; and

a negated AND (NAND) gate configured to output a control signal in response to the output of the inverter delayed by the capacitor and the output of the comparator.

10. The active rectifier of claim 7, wherein the controller comprises:

a comparator configured to adjust a reference voltage by a predetermined offset voltage to advance an output of the comparator by a predetermined period of time, the output being obtained by comparing the input signal to the adjusted reference voltage;

wherein the switch is configured to be activated based on an output of the comparator.

11. The active rectifier of claim 10, wherein the predetermined offset voltage is applied by a resistor divider.

12. The active rectifier of claim 10, wherein the predetermined offset voltage is applied by a diode.

13. An active rectifier comprising:

a first loop configured to store a power of an interval in which an input signal has a positive phase; and

a second loop configured to store a power of an interval in which the input signal has a negative phase;

wherein each of the first loop and the second loop is further configured to deactivate a switch configured to control the active rectifier in response to a predetermined time delay elapsing from a point in time at which the switch is activated to compensate for reverse current leakage,

wherein the first loop is further configured to detect a rising edge of the input signal and output a control signal based on the rising edge and a signal delayed from the rising edge.

14. The active rectifier of claim 13, wherein the first loop comprises:

a first switch configured to enable a current to flow in the first loop in response to the input signal in the interval in which the input signal has the positive phase; and

a first delay switch configured to interrupt a current flowing in the first loop in the interval in which the input signal has the positive phase in response to a predetermined time delay elapsing from a point in time at which the first delay switch is activated.

15. The active rectifier of claim 14, wherein the first delay switch comprises:

a rising edge detector configured to detect the rising edge of the input signal;

a delay unit configured to output the signal delayed from the rising edge by the predetermined time delay; and

a set-reset (SR) latch configured to output the control signal in response to the rising edge and the signal delayed from the rising signal.

16. The active rectifier of claim 14, wherein the first delay switch comprises:

a comparator configured to output a comparison result obtained by comparing the input signal to a reference voltage;

an inverter configured to invert the output of the comparator;

a capacitor configured to delay an output of the inverter by the predetermined time delay; and

a negated AND (NAND) gate configured to output a control signal in response to the output of the inverter delayed by the capacitor and the output of the comparator.

17. The active rectifier of claim 13, wherein the second loop comprises:

a second switch configured to enable a current to flow in the second loop in response to the input signal in the interval in which the input signal has the negative phase; and

a second delay switch configured to interrupt a current flowing in the second loop in the interval in which the input signal has the negative phase in response to a predetermined time delay elapsing from a point in time at which the second delay switch is activated.

18. The active rectifier of claim 17, wherein the second delay switch comprises:

a rising edge detector configured to detect a rising edge of the input signal;

a delay unit configured to output a signal delayed from the rising edge by the predetermined time delay; and

a set-reset (SR) latch configured to output a control signal in response to the rising edge and the signal delayed from the rising edge.

19. The active rectifier of claim 17, wherein the second delay switch comprises:

a comparator configured to output a comparison result obtained by comparing the input signal to a reference voltage;

an inverter configured to invert the output of the comparator;

a capacitor configured to delay an output of the inverter by the predetermined time delay; and

a negated AND (NAND) gate configured to output a control signal in response to the output of the inverter delayed by the capacitor and the output of the comparator.

20. A circuit for compensating for reverse current leakage in an active rectifier, the circuit comprising:

a switch configured to control a flow of current in the active rectifier; and

a controller configured to turn off the switch to interrupt a current flowing in the active rectifier while compensating for a switch turn-off delay time of the controller to compensate for reverse current leakage in the active rectifier,

wherein the controller is further configured to turn off the switch after a predetermined time delay has elapsed after the switch was turned on,

wherein the controller is further configured to detect a rising edge and output a control signal based on the rising edge and a signal delayed from the rising edge.

21. The circuit of claim 20, wherein the controller comprises a comparator configured to compare an input voltage of the active rectifier to a reference voltage;

and

the predetermined time delay is selected so that the switch is turned off at a point in time at which the input voltage is equal to the reference voltage to compensate for the switch turn-off delay time of the active rectifier and compensate for the reverse current leakage in the active rectifier.

22. The circuit of claim 20, wherein the controller is further configured to turn on the switch to enable a current to flow in the active rectifier while compensating for a switch turn-on delay time of the controller to increase a power conversion efficiency of the active rectifier.

23. The circuit of claim 22, wherein the controller comprises:

a comparator configured to compare an input voltage of the active rectifier to a reference voltage; and

a reference voltage adjuster configured to apply a predetermined offset voltage to the reference voltage;

the controller is further configured to turn on the switch based on an output of the comparator; and

the predetermined offset voltage is selected so that the switch is turned on at a point in time at which the input voltage is equal to the reference voltage to increase the power conversion efficiency of the active rectifier and compensate for the switch turn-on delay time of the controller.