Apparatus and methods for biasing radio frequency switches

• US 9,712,158 B1
• Filed: 04/07/2016
• Issued: 07/18/2017
• Est. Priority Date: 04/07/2016
• Status: Active Grant

• Current Assignee: Analog Devices International Unlimited Company (Analog Devices, Inc.)
• Original Assignee: Analog Devices Global Unlimited Company (Analog Devices, Inc.)
• Inventors: Serttek, Ozgun, Cavus, Bilal Tarik
• Primary Examiner(s): O'Neill, Patrick
• Application Number:
  US15/092,975
• Time in Patent Office: 467 Days
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 17/6871 the output circuit comprising more than one controlled field-effect transistor
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00

Abstract

Apparatus and methods for biasing radio frequency (RF) switches are provided herein. In certain configurations, an RF switching circuit includes a field effect transistor (FET) switch electrically connected between a first terminal and a second terminal, and an adaptive biasing circuit that generates a bias voltage used in part to bias a gate of the FET switch. The adaptive biasing circuit includes a low pass filter that generates a low pass filtered voltage based on low pass filtering a voltage of the first terminal, a buffer circuit that receives the low pass filtered voltage and generates a buffered voltage, and a voltage shifting circuit that generates the bias voltage by shifting the buffered voltage by an amount of voltage that depends on a state of a switch control signal.

Claims

1. A radio frequency (RF) switching circuit comprising:

a field effect transistor (FET) switch electrically connected along a signal path; and

an adaptive biasing circuit configured to generate a bias voltage, wherein a gate of the FET switch is biased in part by the bias voltage, the adaptive biasing circuit comprising;

a low pass filter configured to generate a low pass filtered voltage based on low pass filtering a signal path voltage of a node of the signal path;

a buffer circuit configured to receive the low pass filtered voltage and to generate a buffered voltage; and

a voltage shifting circuit configured to generate the bias voltage by shifting the buffered voltage by an amount of voltage that changes based on a state of a switch control signal.

2. The RF switching circuit of claim 1, further comprising a gate resistor, wherein the gate of the FET switch receives the bias voltage via the gate resistor.

3. The RF switching circuit of claim 2, wherein a low frequency component of the signal path voltage is provided to the gate of the FET switch via the bias voltage.

4. The RF switching circuit of claim 3, wherein a high frequency component of the signal path voltage is provided to the gate of the FET switch via a parasitic capacitance of the FET switch.

5. The RF switching circuit of claim 1, wherein the buffer circuit comprises a FET source follower circuit.

6. The RF switching circuit of claim 5, wherein the voltage shifting circuit generates the bias voltage by controlling an amount of bias current of the FET source follower circuit based on the state of the switch control signal.

7. The RF switching circuit of claim 1, wherein the FET switch comprises a depletion mode field effect transistor (DFET) switch having a threshold voltage that is less than or equal to about 0 V.

8. The RF switching circuit of claim 7, wherein the buffer circuit comprises a first DFET and a first resistor, wherein a gate of the first DFET receives the low pass filtered voltage, and wherein a source of the first DFET is electrically connected to a first end of the first resistor.

9. The RF switching circuit of claim 8, wherein the voltage shifting circuit comprises a first current source comprising a second DFET and a second resistor, wherein a gate of the second DFET is electrically connected to a first voltage, wherein a source of the second DFET is electrically connected to the first voltage via the second resistor, and wherein a drain of the second DFET is electrically connected to a second end of the first resistor.

10. The RF switching circuit of claim 9, wherein the voltage shifting circuit further comprises a second current source and a switch electrically connected in series between the second end of the first resistor and the first voltage, wherein the switch is controlled based on the state of the switch control signal.

11. The RF switching circuit of claim 1, wherein the FET switch and the adaptive biasing circuit are integrated on a compound semiconductor die.

12. An electronically-implemented method of switch biasing, the method comprising:

receiving a switch control signal and a voltage of a signal path as inputs to an adaptive biasing circuit;

generating a low pass filtered voltage by low pass filtering the voltage of the signal path using the adaptive biasing circuit;

generating a buffered voltage based on buffering the low pass filtered voltage using the adaptive biasing circuit;

generating a bias voltage using the adaptive biasing circuit by shifting the buffered voltage by an amount of voltage that changes based on a state of the switch control signal; and

controlling a gate voltage of a FET switch that is electrically connected along the signal path based in part on the bias voltage.

13. The method of claim 12, further comprising:

providing a low frequency component of the voltage of the signal path to the gate of the FET switch via the bias voltage; and

providing a low frequency component of the voltage of the signal path to the gate of the FET switch via a parasitic capacitance of the FET switch.

14. A radio frequency (RF) system comprising:

one or more series field effect transistor (FET) switches electrically connected along a signal path between a first terminal and a second terminal; and

a first adaptive biasing circuit configured to generate a first bias voltage, wherein a first series FET switch of the one or more series FET switches is biased in part by the first bias voltage, wherein the first adaptive biasing circuit comprises;

a low pass filter configured to generate a low pass filtered voltage based on low pass filtering a voltage of the first terminal;

a buffer circuit configured to receive the low pass filtered voltage and to generate a buffered voltage; and

a voltage shifting circuit configured to generate the first bias voltage based on the buffered voltage and a state of a switch control signal.

15. The RF system of claim 14, wherein the one or more series FET switches comprises a plurality of series FET switches electrically connected in series between the first terminal and the second terminal.

16. The RF system of claim 15, further comprising a second adaptive biasing circuit configured to generate a second bias voltage that is based on a voltage of the second terminal, wherein a second series FET switch of the plurality of series FET switches is biased in part by the second bias voltage.

17. The RF system of claim 16, further comprising a voltage divider that receives the first bias voltage and the second bias voltage and generates a plurality of divided voltages that bias the plurality of series FET switches.

18. The RF system of claim 15, wherein the plurality of series FET switches are biased by a plurality of adaptive biasing circuits each connected to a different node along the signal path.

19. The RF system of claim 14, further comprising one or more shunt FET switches electrically connected in shunt to the signal path.

20. The RF system of claim 19, further comprising a second adaptive biasing circuit configured to generate a second bias voltage that is based on a voltage of a node of the signal path, wherein the one or more shunt FET switches are biased in part by the second bias voltage.