Low read data storage management

• US 9,715,939 B2
• Filed: 10/28/2015
• Issued: 07/25/2017
• Est. Priority Date: 08/10/2015
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Higgins, James M., Ellis, Robert W.
• Primary Examiner(s): LE, TOAN K
• Application Number:
  US14/925,945
• Publication Number:
  US 20170047124A1
• Time in Patent Office: 636 Days
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0622 in relation to access
• CPC Class Codes: G06F 3/0637 Permissions
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles

Abstract

Systems and methods disclosed herein are used to efficiently manage low read data. In one aspect, a method includes, in response to detecting occurrence of a first event (e.g., PFail), writing low read data to non-volatile memory of a storage device with a fast SLC programming mode, distinct from a default SLC programming mode. Writing the low read data with the fast SLC programming mode: (i) includes using one or more memory programming parameters distinct from a default set of memory programming parameters used for writing data with the default SLC programming mode and (ii) takes less time per predefined unit of data than writing data with the default SLC programming mode. The method also includes: in response to detecting occurrence of a second event (e.g., host write command), writing data corresponding to the second event with the default SLC programming mode using the default set of memory programming parameters.

Claims

1. A method of managing a storage device that includes non-volatile memory, the method comprising:

detecting occurrence of a first event;

in response to detecting the occurrence of the first event, writing low read data to the non-volatile memory of the storage device with a fast single-level cell (SLC) programming mode, distinct from a default SLC programming mode, wherein;

low read data is data satisfying predefined low read criteria,

writing data with the fast SLC programming mode includes writing data with a density of one data bit per memory cell using one or more memory programming parameters distinct from a default set of memory programming parameters used for writing data with the default SLC programming mode, and

writing data with the fast SLC programming mode takes less time per predefined unit of data than writing data with the default SLC programming mode;

detecting occurrence of a second event; and

in response to detecting the occurrence of the second event, writing data corresponding to the second event to the non-volatile memory of the storage device with the default SLC programming mode, wherein writing data with the default SLC programming mode includes writing data with a density of one data bit per memory cell using the default set of memory programming parameters.

2. The method of claim 1, wherein writing data to the non-volatile memory of the storage device with the fast SLC programming mode takes at least 40% less time per predefined unit of data as compared to writing data to the non-volatile memory of the storage device with the default SLC programming mode.

3. The method of claim 1, wherein:

writing data with the fast SLC programming mode includes a memory programming operation comprising a plurality of electrical pulses, and

the one or more memory programming parameters used for writing data with the fast SLC programming mode include one or more parameters selected from the group consisting of;

a clock rate or programming pulse duration, a maximum number of electrical pulses used in the memory programming operation, a first electrical pulse or first set of electrical pulses of the plurality of electrical pulses, a write verification control parameter, and a delta voltage corresponding to a difference between a second voltage, for a second electrical pulse or second set of electrical pulses of the plurality of electrical pulses, and the first voltage.

4. The method of claim 3, wherein the clock rate or programming pulse duration used in the fast SLC programming mode is less than the clock rate or programming pulse duration used in the default SLC programming mode.

5. The method of claim 3, wherein the number of electrical pulses within the plurality of electrical pulses is lower than a default number of electrical pulses within a default plurality of electrical pulses.

6. The method of claim 5, wherein the first voltage for the first electrical pulse is greater than a default voltage for each electrical pulse within the default plurality of electrical pulses.

7. The method of claim 1, wherein the first event is a power failure event, a scheduled write event for copying at least a portion of a mapping table to the non-volatile memory of the storage device, an event indicating log fullness, or an event requiring dumping of an error log.

8. The method of claim 1, wherein writing data with the fast SLC programming mode includes:

retrieving the one or more memory programming parameters from volatile memory; and

adjusting at least one of the one or more memory programming parameters in accordance with an age metric or a performance metric associated with the non-volatile memory of the storage device.

9. The method of claim 1, further comprising:

reserving a portion of the non-volatile memory of the storage device; and

configuring the reserved portion of the non-volatile memory of the storage device to write data with the fast SLC programming mode.

10. The method of claim 9, wherein the reserving and the configuring occur prior to detecting occurrence of the first event.

11. The method of claim 1, wherein the predefined low read criteria comprise a criterion that an estimated number of read operations for reading the low read data is below a predefined threshold number of read operations and/or a criterion that the low read data can be stored with low endurance.

12. A storage device, comprising:

non-volatile memory; and

a storage controller, the storage controller including one or more controller modules configured to;

detect occurrence of a first event;

in response to detecting the occurrence of the first event, write low read data to the non-volatile memory of the storage device, wherein low read data is data satisfying predefined low read criteria, wherein;

writing the low read data includes writing the low read data to the non-volatile memory of the storage device with a fast single-level cell (SLC) programming mode, distinct from a default SLC programming mode to the non-volatile memory of the storage device,

writing data with the fast SLC programming mode includes writing the low read data with a density of one data bit per memory cell using one or more memory programming parameters distinct from a default set of memory programming parameters for writing data to the non-volatile memory of the storage device with the default SLC programming mode, and

writing data to the non-volatile memory of the storage device with the fast SLC programming mode takes less time per predefined unit of data than writing data to the non-volatile memory of the storage device with the default SLC programming mode;

detect occurrence of a second event; and

in response to detecting the occurrence of the second event, write data corresponding to the second event to the non-volatile memory of the storage device with the default SLC programming mode with a density of one data bit per memory cell using the default set of memory programming parameters.

13. The storage device of claim 12, wherein the one or more controller modules include:

an event occurrence detection module to detect occurrence of the first and the second events; and

a data write module to write data to the non-volatile memory with the fast SLC programming mode in response to detecting the occurrence of the first event;

wherein the data write module is configured to write data corresponding to the second event to the non-volatile memory with the default SLC programming mode using the default set of memory programming parameters in response to detecting occurrence of the second event.

14. The storage device of claim 12, wherein writing data to the non-volatile memory of the storage device with the fast SLC programming mode takes at least 40% less time per predefined unit of data as compared to writing data to the non-volatile memory of the storage device with the default SLC programming mode.

15. The storage device of claim 12, wherein:

writing data with the fast SLC programming mode includes a memory programming operation comprising a plurality of electrical pulses, and

the one or more memory programming parameters used for writing data with the fast SLC programming mode include one or more parameters selected from the group consisting of;

a clock rate or programming pulse duration, a maximum number of electrical pulses used in the memory programming operation, a first electrical pulse or first set of electrical pulses of the plurality of electrical pulses, a write verification control parameter, and a delta voltage corresponding to a difference between a second voltage, for a second electrical pulse or second set of electrical pulses of the plurality of electrical pulses, and the first voltage.

16. The storage device of claim 15, wherein the clock rate or programming pulse duration used in the fast SLC programming mode is less than the clock rate or programming pulse duration used in the default SLC programming mode.

17. The storage device of claim 15, wherein the number of electrical pulses within the plurality of electrical pulses is lower than a default number of electrical pulses within a default plurality of electrical pulses.

18. A non-transitory computer-readable storage medium, storing one or more programs configured for execution by one or more processors of a storage device, the one or more programs including instructions that when executed by the one or more processors cause the storage device to:

detect occurrence of a first event;

in response to detecting the occurrence of the first event, write low read data to the non-volatile memory of the storage device, wherein low read data is data satisfying predefined low read criteria, wherein;

writing the low read data includes writing the low read data to the non-volatile memory of the storage device with a fast single-level cell (SLC) programming mode, distinct from a default SLC programming mode to the non-volatile memory of the storage device,

writing data with the fast SLC programming mode includes writing the low read data with a density of one data bit per memory cell using one or more memory programming parameters distinct from a default set of memory programming parameters for writing data to the non-volatile memory of the storage device with the default SLC programming mode, and

writing data to the non-volatile memory of the storage device with the fast SLC programming mode takes less time per predefined unit of data than writing data to the non-volatile memory of the storage device with the default SLC programming mode;

detect occurrence of a second event; and

in response to detecting the occurrence of the second event, write data corresponding to the second event to the non-volatile memory of the storage device with the default SLC programming mode with a density of one data bit per memory cell using the default set of memory programming parameters.

19. The non-transitory computer-readable storage medium of claim 18, wherein the storage device includes a storage controller that includes the one or more processors, the one or more programs include one or more controller modules configured for execution by the one or more processors of the storage controller, and the one or more controller modules include:

an event occurrence detection module to detect occurrence of the first and the second events; and

a data write module to write data to the non-volatile memory with the fast SLC programming mode in response to detecting the occurrence of the first event;

wherein the data write module is configured to write data corresponding to the second event to the non-volatile memory with the default SLC programming mode using the default set of memory programming parameters in response to detecting occurrence of the second event.