Bias control for stacked transistor configuration

• US 9,716,477 B2
• Filed: 02/19/2015
• Issued: 07/25/2017
• Est. Priority Date: 12/28/2012
• Status: Active Grant

• Current Assignee: pSemi Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Wagh, Poojan, Golat, Joseph, Olson, Chris, Kovac, David, Dykstra, Jeffrey A.
• Primary Examiner(s): NGUYEN, KHIEM D
• Application Number:
  US14/626,833
• Publication Number:
  US 20150270806A1
• Time in Patent Office: 887 Days
• Field of Search: 330127, 330296, 330297
• CPC Class Codes: H03F 1/0227 using supply converters
• CPC Class Codes: H03F 1/0244 Stepped control
• CPC Class Codes: H03F 1/025 by using a signal derived from the input signal
• CPC Class Codes: H03F 1/0277 Selecting one or more amplifiers from a plurality of amplifiers
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 1/3247 using feedback acting on predistortion circuits H03F1/3264 takes precedence
• CPC Class Codes: H03F 1/3282 Acting on the phase and the amplitude of the input signal
• CPC Class Codes: H03F 1/56 Modifications of input or output impedances, not otherwise provided for
• CPC Class Codes: H03F 2200/102 A non-specified detector of a signal envelope being used in an amplifying circuit
• CPC Class Codes: H03F 2200/108 A coil being added in the drain circuit of a FET amplifier stage, e.g. for noise reducing purposes
• CPC Class Codes: H03F 2200/15 the supply or bias voltage or current at the drain side of a FET being continuously controlled by a controlling signal
• CPC Class Codes: H03F 2200/18 the bias of the gate of a FET being controlled by a control signal
• CPC Class Codes: H03F 2200/222 A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
• CPC Class Codes: H03F 2200/336 A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit
• CPC Class Codes: H03F 2200/387 A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/408 the output amplifying stage of an amplifier comprising three power stages
• CPC Class Codes: H03F 2200/411 the output amplifying stage of an amplifier comprising two power stages
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2200/534 Transformer coupled at the input of an amplifier
• CPC Class Codes: H03F 2200/537 A transformer being used as coupling element between two amplifying stages
• CPC Class Codes: H03F 2200/541 : Transformer coupled at the output of an amplifier
• CPC Class Codes: H03F 2200/61 : the cascode amplifier has more than one common gate stage
• CPC Class Codes: H03F 2200/78 : A comparator being used in a controlling circuit of an amplifier
• CPC Class Codes: H03F 2201/3233 : Adaptive predistortion using lookup table, e.g. memory, RAM, ROM, LUT, to generate the predistortion
• CPC Class Codes: H03F 2203/21127 : the input bias current of a power amplifier being controlled, e.g. by an active current source or a current mirror
• CPC Class Codes: H03F 2203/45366 : the AAC comprising multiple transistors parallel coupled at their gates only, e.g. in a cascode dif amp, only those forming the composite common source transistor
• CPC Class Codes: H03F 2203/45544 : the IC comprising one or more capacitors, e.g. coupling capacitors
• CPC Class Codes: H03F 2203/45638 : the LC comprising one or more coils
• CPC Class Codes: H03F 2203/45731 : the LC comprising a transformer
• CPC Class Codes: H03F 3/195 : in integrated circuits
• CPC Class Codes: H03F 3/211 : using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/24 : of transmitter output stages
• CPC Class Codes: H03F 3/45183 : Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45188 : Non-folded cascode stages

Abstract

Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are presented, where the amplifier can be an envelope tracking amplifier. Circuital arrangements to generate reference gate-to-source voltages for biasing of the gates of the transistors of the stack are also presented. Particular biasing for a case of an input transistor of the stack is also presented.

Claims

1. A circuital arrangement comprising:

i) an amplifier comprising;

stacked transistors having a plurality of bias terminals comprising a plurality of gate terminals of the stacked transistors and a drain terminal of an output transistor of the stacked transistors;

an input port operatively connected to an input transistor of the stacked transistors;

an output port operatively connected to the drain terminal of the output transistor; and

a reference terminal operatively coupling the input transistor to a reference potential,

wherein;

the stacked transistors comprise two subsets of transistors operatively arranged in series, a first subset comprising the input transistor operatively connected between the reference potential at the reference terminal and a second subset, the second subset comprising one or more transistors operatively connected in series with each other, at least one transistor of the one or more transistors being the output transistor, the second subset operatively connected between the first subset and a variable output supply bias voltage or current provided to the output transistor, the variable output supply bias voltage or current being based on an envelope signal of an RF signal at the input port; and

ii) a gate bias circuit,

wherein;

the gate bias circuit is configured to operatively provide at a gate terminal of each transistor of the one or more transistors of the second subset a dynamic bias voltage which is a gate DC offset voltage above a voltage at a source terminal of the each transistor, the gate DC offset voltage being based on a gate-to-source voltage of the each transistor, and the voltage at the source terminal of the each transistor being based on a distribution of a voltage at the drain terminal of the output transistor across the stacked transistors.

2. The circuital arrangement according to claim 1, wherein the voltage at the drain terminal of the output transistor is based on the variable output supply bias voltage or current provided to the output transistor.

3. The circuital arrangement according to claim 1, further comprising one or more gate capacitors connected between the gate terminals of the one or more transistors of the second subset and the reference potential.

4. The circuital arrangement according to claim 3, wherein capacitance values of the one or more gate capacitors are based on an operating frequency of an RF signal at the input port.

5. The circuital arrangement according to any one of claims 1-3, wherein the distribution is an equal distribution of the voltage at the drain terminal of the output transistor across the stacked transistors.

6. The circuital arrangement according to any one of claims 1-3, wherein the distribution provides a voltage across the output transistor which is higher than a voltage across other transistors of the stacked transistors.

7. The circuital arrangement according to any one of claims 1-3, wherein the distribution provides a voltage across the input transistor which is higher than a voltage across other transistors of the stacked transistors.

8. The circuital arrangement according to any one of claims 1-3, wherein the gate DC offset voltage is one or a fraction of the gate-to-source voltage of the each transistor.

9. The circuital arrangement according to any one of claims 1-3, further comprising a filter configured to provide at the gate terminal of each transistor of the one or more transistors of the second subset a filtered bias voltage based on a filtered version of the variable output supply bias voltage or current, wherein a voltage at the gate terminal of the each transistor is the sum of the filtered bias voltage and the dynamic bias voltage.

10. The circuital arrangement according to claim 9, wherein a cutoff frequency of the filter is based on a geometric mean of an operating frequency of an RF signal at the input port and an upper frequency of the variable supply bias voltage or current.

11. The circuital arrangement according to claim 10, wherein the operating frequency is about 700 MHz, the upper frequency of the variable supply bias voltage or current is about 30 MHz and the cutoff frequency is about 145 MHz.

12. The circuital arrangement according to claim 10, wherein the filter is one of:

a) a low pass filter, b) a pass band filter, and c) a band reject filter.

13. The circuital arrangement according to claim 9, wherein the further circuitry comprises one or more series connected resistive-capacitive (RC) networks operatively coupled between gate terminals of the one or more transistors of the one or more transistors of the second subset and the variable output supply bias voltage or current.

14. A circuital arrangement comprising:

i) an amplifier comprising;

stacked transistors having a plurality of bias terminals comprising a plurality of gate terminals of the stacked transistors and a drain terminal of an output transistor of the stacked transistors;

an input port operatively connected to an input transistor of the stacked transistors;

an output port operatively connected to the drain terminal of the output transistor; and

a reference terminal operatively coupling the input transistor to a reference potential,

wherein;

the stacked transistors comprise two subsets of transistors operatively arranged in series, a first subset comprising the input transistor operatively connected between the reference potential at the reference terminal and a second subset, the second subset comprising one or more transistors operatively connected in series with each other, at least one transistor of the one or more transistors being the output transistor, the second subset operatively connected between the first subset and a variable output supply bias voltage or current provided to the output transistor; and

ii) a gate bias circuit configured to operatively provide at a gate terminal of each transistor of the one or more transistors of the second subset a dynamic bias voltage which is a gate DC offset voltage above a voltage at a source terminal of the each transistor, the gate DC offset voltage being based on a gate-to-source voltage of the each transistor, and the voltage at the source terminal of the each transistor being based on a distribution of a voltage at the drain terminal of the output transistor across the stacked transistors, the gate bias circuit comprising;

a resistor voltage divider operatively coupled between the variable output supply bias voltage or current and the reference potential, wherein nodes of the resistor voltage divider are coupled to the gate terminal of the each transistor of the one or more transistors of the second subset; and

one or more current sources operatively coupled to one or more nodes of the resistor voltage divider,

wherein;

the resistor voltage divider provides voltages at the gate terminals of the each transistor of the one or more transistors of the second subset which are based on the distribution of the voltage at the drain terminal of the output transistor, and

the one or more current sources provide the gate DC offset voltage at the gate terminal of the each transistor of the one or more transistors of the second subset.

15. The circuital arrangement according to claim 14, wherein nodes of the resistor voltage divider are coupled to the gate terminal of the each transistor via a series connected resistor.

16. The circuital arrangement according to claim 14, wherein nodes of the resistor voltage divider further comprise capacitance to provide low filtering of the voltages provided by the resistor voltage divider.

17. The circuital arrangement according to claim 16, wherein the capacitance is associated to:

a) a capacitor connected to the node, b) an output capacitance of the one or more current sources, or c) a combination of a) and b).

18. The circuital arrangement according to claim 14, wherein a value of a current injected by a current source of the one or more current sources into a node of the resistor voltage divider is based on a gate-to-source value of a transistor of the one or more transistors of the second subset and a resistor value of a resistor of the resistor divider.

19. The circuital arrangement according to claim 18, wherein the current source comprises a reference transistor with a same device characteristics as the transistor associated with the gate-to-source value.

20. The circuital arrangement according to claim 19, wherein a drain-to-source voltage of the reference transistor is substantially equal to a drain-to-source voltage of the transistor associated with the gate-to-source value.

21. The circuital arrangement according to claim 14, wherein a current source of the one or more current sources is coupled to a corresponding node of the resistor voltage divider via a series connected resistor.

22. The circuital arrangement according to claim 14, wherein a current source of the one or more current sources further comprises a shunt capacitor connected at an output of the current source.

23. The circuital arrangement according to claim 14, wherein a current source of the one or more current sources comprises an auto-select supply voltage circuit, wherein the auto-select supply voltage circuit is operatively configured to automatically provide an output stage of the current source with a supply voltage based on a larger voltage of a first supply voltage and a second supply voltage, wherein the output stage of the current source provides an output current of the current source.

24. The circuital arrangement according to claim 23, wherein the first supply voltage is a battery voltage or a regulated voltage based on the battery voltage.

25. The circuital arrangement according to claim 24, wherein the second supply voltage is a voltage based on the variable output supply bias voltage or current provided to the output transistor.

26. The circuital arrangement according to claim 25, wherein the auto-select supply voltage circuit comprises:

a first current mirror operatively coupled to the first supply voltage; and

a second current mirror operatively coupled to the second supply voltage,

wherein;

an output current terminal of the first current mirror is connected to an output current terminal of the second current mirror, and

an output reference current terminal of the first current mirror is connected to an output reference current terminal of the second current mirror.

27. The circuital arrangement according to claim 26, wherein the first current mirror and the second current mirror comprise transistors with a same device characteristics.

28. The circuital arrangement according to claim 27, further comprising:

a first diode operatively connected between the first supply voltage and a body node; and

a second diode operatively connected between the second supply voltage and the body node,

wherein bodies of the first current mirror and the second current mirror transistors are tied together at the body node.

29. The circuital arrangement according to claim 28, wherein the first diode and the second diode are diode-connected transistors.

30. The circuital arrangement according to claim 29, wherein the diode-connected transistors are zero-threshold P-type metal-oxide-semiconductor field effect transistors (P-MOSFETs).

31. The circuital arrangement according to claim 26, wherein the second current mirror is operatively coupled to the second supply voltage via one of or a combination of:

a) a series connected resistor, and b) a shunt connected capacitor.

32. The circuital arrangement according to claim 31, wherein the combination of a) and b) provides a filter whose cutoff frequency is based on a frequency content of the second supply voltage.

33. A circuital arrangement comprising:

i) an amplifier comprising;

stacked transistors having a plurality of bias terminals comprising a plurality of gate terminals of the stacked transistors and a drain terminal of an output transistor of the stacked transistors;

an input port operatively connected to an input transistor of the stacked transistors;

an output port operatively connected to the drain terminal of the output transistor; and

a reference terminal operatively coupling the input transistor to a reference potential,

wherein;

the stacked transistors comprise two subsets of transistors operatively arranged in series, a first subset comprising the input transistor operatively connected between the reference potential at the reference terminal and a second subset, the second subset comprising one or more transistors operatively connected in series with each other, at least one transistor of the one or more transistors being the output transistor, the second subset operatively connected between the first subset and a variable output supply bias voltage or current provided to the output transistor; and

ii) a gate bias circuit configured to operatively provide at a gate terminal of each transistor of the one or more transistors of the second subset a dynamic bias voltage which is a gate DC offset voltage above a voltage at a source terminal of the each transistor, the gate DC offset voltage being based on a gate-to-source voltage of the each transistor, and the voltage at the source terminal of the each transistor being based on a distribution of a voltage at the drain terminal of the output transistor across the stacked transistors, wherein the gate bias circuit comprises;

a resistor-diode voltage divider coupled between the variable output supply bias voltage or current and the reference potential, wherein nodes of the resistor-diode voltage divider are coupled to the gate terminal of the each transistor of the one or more transistors of the second subset, the resistor-diode divider comprising a series connected resistor and diode-connected transistor between any two nodes of the resistor-diode divider.

34. The circuital arrangement according to claim 33, wherein a gate and a drain of the diode-connected transistor are connected to a same node of the resistor-diode voltage divider and wherein the diode-connected transistor has a same device characteristics as a transistor of the one or more transistors of the second subset associated to a gate terminal coupled to the same node.

35. The circuital arrangement according to claim 34, wherein nodes of the resistor-diode voltage divider are coupled to the gate terminal of the each transistor via a series connected resistor.

36. A circuital arrangement comprising:

i) an amplifier comprising;

stacked transistors having a plurality of bias terminals comprising a plurality of gate terminals of the stacked transistors and a drain terminal of an output transistor of the stacked transistors;

an input port operatively connected to an input transistor of the stacked transistors;

an output port operatively connected to the drain terminal of the output transistor; and

a reference terminal operatively coupling the input transistor to a reference potential,

wherein;

the stacked transistors comprise two subsets of transistors operatively arranged in series, a first subset comprising the input transistor operatively connected between the reference potential at the reference terminal and a second subset, the second subset comprising one or more transistors operatively connected in series with each other, at least one transistor of the one or more transistors being the output transistor, the second subset operatively connected between the first subset and a variable output supply bias voltage or current provided to the output transistor; and

ii) a gate bias circuit configured to operatively provide at a gate terminal of each transistor of the one or more transistors of the second subset a dynamic bias voltage which is a gate DC offset voltage above a voltage at a source terminal of the each transistor, the gate DC offset voltage being based on a gate-to-source voltage of the each transistor, and the voltage at the source terminal of the each transistor being based on a distribution of a voltage at the drain terminal of the output transistor across the stacked transistors, wherein the gate bias circuit comprises;

stacked voltage regulators coupled in a parallel configuration with a replica circuit of the stacked transistors, wherein;

each voltage regulator of the stacked voltage regulators provides a regulated voltage at a source terminal of a transistor of a second subset transistors of the replica circuit, the regulated voltage being based on the distribution of the voltage at the drain terminal of the output transistor, and

the replica circuit provides the gate DC offset voltage.

37. The circuital arrangement according to claim 36, wherein:

a voltage regulator of the stacked voltage regulators comprises an operational transconductance amplifier comprising a differential input and a single ended output,

a gate of a corresponding transistor of the second subset transistors of the replica circuit is connected to the single ended output, and

a source of the corresponding transistor is connected to an input of the differential input.

38. A circuital arrangement comprising:

i) an amplifier comprising;

stacked transistors having a plurality of bias terminals comprising a plurality of gate terminals of the stacked transistors and a drain terminal of an output transistor of the stacked transistors;

an input port operatively connected to an input transistor of the stacked transistors;

an output port operatively connected to the drain terminal of the output transistor; and

a reference terminal operatively coupling the input transistor to a reference potential,

wherein;

the stacked transistors comprise two subsets of transistors operatively arranged in series, a first subset comprising the input transistor operatively connected between the reference potential at the reference terminal and a second subset, the second subset comprising one or more transistors operatively connected in series with each other, at least one transistor of the one or more transistors being the output transistor, the second subset operatively connected between the first subset and a variable output supply bias voltage or current provided to the output transistor; and

ii) a gate bias circuit configured to operatively provide at a gate terminal of each transistor of the one or more transistors of the second subset a dynamic bias voltage which is a gate DC offset voltage above a voltage at a source terminal of the each transistor, the gate DC offset voltage being based on a gate-to-source voltage of the each transistor, and the voltage at the source terminal of the each transistor being based on a distribution of a voltage at the drain terminal of the output transistor across the stacked transistors, wherein the gate bias circuit comprises;

an input transistor gate bias circuit adapted to provide a gate bias voltage at a gate terminal of the input transistor, wherein the gate bias voltage is configured to produce a fixed bias current through the stacked transistors.

39. The circuital arrangement according to claim 38, wherein the input transistor gate bias circuit comprises:

a reference transistor having a size which is a factor 1/N of a size of the input transistor; and

a current source which provides a current of an amplitude equal to 1/N of an amplitude of the fixed bias current,

wherein N is an integer number.

40. The circuital arrangement according to claim 39, wherein a value of N is comprised within a range of 100 to 1000.

41. The circuital arrangement according to claim 39, wherein the value of N is 640.

42. The circuital arrangement according to claim 39, wherein during operation of the circuital arrangement, the input transistor and the reference transistor are configured to have a same drain-to-source voltage value and a same gate bias voltage value.

43. The circuital arrangement according to claim 42, wherein the current flowing through the reference transistor is the current provided by the current source.

44. The circuital arrangement according to claim 43, wherein the input transistor gate bias circuit further comprises a second-subset-replica stacked transistors configured to generate a drain-to-source voltage for the reference transistor.

45. The circuital arrangement according to claim 44, wherein the input transistor gate bias circuit further comprises an operational amplifier, wherein the operational amplifier is configured to generate the gate bias voltage.

46. The circuital arrangement according to claim 45, wherein:

the drain-to-source voltage is provided to a negative input terminal of the operational amplifier;

a positive input terminal of the operational amplifier is connected to a drain terminal of the reference transistor;

a source terminal of the reference transistor is connected to the reference potential; and

an output terminal of the operational amplifier is connected to a gate terminal of the reference transistor.

47. The circuital arrangement according to claim 46, wherein the output terminal of the operational amplifier is further coupled to the gate terminal of the input transistor.

48. The circuital arrangement according to claim 47, wherein a filter is connected between the output terminal of the operational amplifier and the gate terminal of the input transistor.

49. The circuital arrangement according to claim 48, wherein the filter is a low-pass filter configured, during operation of the circuital arrangement, to decouple an RF signal at the input port from the operational amplifier.

50. The circuital arrangement according to claim 46, wherein the second-subset-replica stacked transistors comprises:

a same number transistors as the second subset, operatively connected in series;

a first transistor, operatively connected to the variable output supply bias voltage or current; and

a last transistor, operatively connected to the negative input terminal of the operational amplifier,

wherein transistors of the second-subset-replica stacked transistors are reduced size replica of the one or more transistors of the second subset.

51. The circuital arrangement according to claim 50, wherein the second-subset-replica stacked transistors further comprises a current source operatively connected to the last transistor, wherein the current source is configured to provide a current flow through the second-subset-replica stacked transistors in correspondence of the fixed bias current.

52. The circuital arrangement according to claim 51, wherein an amplitude of the current flow through the second-subset-replica stacked transistors is a factor 1/N of the amplitude of the fixed bias current, wherein N is an integer number.

53. The circuital arrangement according to claim 52, wherein a value of N is comprised within a range of 100 to 1000.

54. The circuital arrangement according to claim 44, wherein the gate bias circuit is further configured to provide at a gate of each transistor of the second-subset-replica stacked transistors a same dynamic bias voltage provided to a corresponding transistor of the second subset.

55. A circuital arrangement comprising:

i) an amplifier comprising;

stacked transistors having a plurality of bias terminals comprising a plurality of gate terminals of the stacked transistors and a drain terminal of an output transistor of the stacked transistors;

an input port operatively connected to an input transistor of the stacked transistors;

an output port operatively connected to the drain terminal of the output transistor; and

a reference terminal operatively coupling the input transistor to a reference potential,

wherein;

the stacked transistors comprise two subsets of transistors operatively arranged in series, a first subset comprising the input transistor operatively connected between the reference potential at the reference terminal and a second subset, the second subset comprising one or more transistors operatively connected in series with each other, at least one transistor of the one or more transistors being the output transistor, the second subset operatively connected between the first subset and a variable output supply bias voltage or current provided to the output transistor, and

the second subset comprises a last transistor operatively connected to the input transistor; and

ii) a gate bias circuit,

wherein;

the gate bias circuit is configured to operatively provide at a gate terminal of a transistor of the one or more transistors of the second subset a dynamic bias voltage which is a gate DC offset voltage above a voltage at a source terminal of the transistor, the gate DC offset voltage being based on a gate-to-source voltage of the transistor, and the voltage at the source terminal of the transistor being based on a distribution of a voltage at the drain terminal of the output transistor across the stacked transistors,

the gate bias circuit provides a fixed bias voltage at a gate terminal of the last transistor, the fixed bias voltage configured to produce a fixed bias current through the stacked transistors, wherein the fixed bias voltage is provided via an operational amplifier, wherein;

a positive input terminal of the operational amplifier is connected to the fixed bias voltage,

a negative input terminal of the operational amplifier is connected to a common node connecting the drain terminal of the input transistor and a source terminal of the last transistor, and

an output terminal coupled to the gate terminal of the last transistor.

56. The circuital arrangement according to claim 55, wherein the output terminal is coupled to the gate terminal of the last transistor via a series resistor and a shunt capacitor.

57. A circuital arrangement comprising:

i) an amplifier comprising;

stacked transistors having a plurality of bias terminals comprising a plurality of gate terminals of the stacked transistors and a drain terminal of an output transistor of the stacked transistors;

an input port operatively connected to an input transistor of the stacked transistors;

an output port operatively connected to the drain terminal of the output transistor; and

a reference terminal operatively coupling the input transistor to a reference potential,

wherein;

the stacked transistors comprise two subsets of transistors operatively arranged in series, a first subset comprising the input transistor operatively connected between the reference potential at the reference terminal and a second subset, the second subset comprising one or more transistors operatively connected in series with each other, at least one transistor of the one or more transistors being the output transistor, the second subset operatively connected between the first subset and a variable output supply bias voltage or current provided to the output transistor,

a first transistor of the stacked transistors is designed for a first performance, and a second transistor of the stacked transistors is designed for a second performance different from the first performance,

the first performance and the second performance are provided by a gate length and/or oxide thickness of the first transistor and the second transistor respectively, and

the second subset comprises a last transistor operatively connected to the input transistor; and

ii) a gate bias circuit,

wherein;

the gate bias circuit is configured to operatively provide at a gate terminal of a transistor of the one or more transistors of the second subset a dynamic bias voltage which is a gate DC offset voltage above a voltage at a source terminal of the transistor, the gate DC offset voltage being based on a gate-to-source voltage of the transistor, and the voltage at the source terminal of the transistor being based on a distribution of a voltage at the drain terminal of the output transistor across the stacked transistors, and

the gate bias circuit provides a fixed bias voltage at a gate terminal of the last transistor.

58. The circuital arrangement according to claim 57, wherein the first transistor is the input transistor, designed for a desired gain, and the second transistor is the last transistor, designed for a higher voltage handling capability than other transistors of the stacked transistors.

59. A method of amplifying a signal in a circuital arrangement, the method comprising:

providing an amplifier comprising stacked transistors in a cascode configuration;

adapting the arrangement to operatively connect a plurality of bias supplies to a plurality of gate terminals of the stacked transistors and to a drain terminal of an output transistor of the stacked transistors;

applying an input signal to an input port of the arrangement operatively connected to an input transistor of the stacked transistors;

varying the bias supply to the drain terminal of the output transistor;

impressing a an amplification on the input signal to obtain an amplified output signal by varying at least one bias supply of the plurality of bias supplies to a gate terminal of a transistor of the stacked transistors;

based on the varying the at least one bias supply, providing a voltage at the gate terminal of the transistor which is a gate DC offset voltage above a voltage at a source terminal of the transistor, the gate DC offset voltage being based on a gate-to-source voltage of the transistor, and the voltage at the source terminal of the transistor being based on a distribution of a voltage at the drain terminal of the output transistor across the stacked transistors;

providing, via a local feedback arrangement, a bias supply of the plurality of bias supplies to a gate terminal of a transistor of the stacked transistors connected to the input transistor; and

based on the providing via the local feedback arrangement, providing a fixed bias current through the stacked transistors,

wherein the varying the bias supply to the drain of the output transistor is based on an envelope signal of the input signal applied to the input port of the circuital arrangement.

60. The method of claim 59, wherein the distribution is an equal distribution of the voltage at the drain terminal of the output transistor across the stacked transistors.

61. The method of claim 59, wherein the distribution provides a voltage across the output transistor which is higher than a voltage across other transistors of the stacked transistors.

62. The method of claim 59, wherein the distribution provides a voltage across the input transistor which is higher than a voltage across other transistors of the stacked transistors.

63. The method of claim 59, wherein the gate DC offset voltage is one or a fraction of the gate-to-source voltage of the transistor.

64. The method of claim 59, further comprising:

providing a fixed bias supply of the plurality of bias supplies to a gate terminal of a transistor of the stacked transistors connected to the input transistor; and

based on the providing a fixed bias supply, providing a fixed bias current though the stacked transistors.

65. The method of claim 64, wherein a gate length and/or oxide thickness of the transistor of the stacked transistors connected to the input transistor is selected to provide a higher voltage handling of the transistor.

66. The method of claim 59, wherein the local feedback arrangement comprises an operational amplifier configured to adjust a voltage at the gate terminal of the transistor of the stacked transistors connected to the input transistor based on a feedback voltage at the source terminal of said transistor.