Semiconductor device

• US 9,735,285 B2
• Filed: 10/18/2016
• Issued: 08/15/2017
• Est. Priority Date: 10/21/2009
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Harada, Hikaru, Yamazaki, Shunpei, Tsubuku, Masashi, Noda, Kosei, Toyotaka, Kouhei, Watanabe, Kazunori
• Primary Examiner(s): Gupta, Raj R
• Application Number:
  US15/296,432
• Publication Number:
  US 20170040459A1
• Time in Patent Office: 301 Days
• CPC Class Codes: G06F 15/76 Architectures of general purpose stored program computers with program plugboard G06F15/08; multicomputers G06F15/16
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/125 the MOSFET being a thin film transistor [TFT]
• CPC Class Codes: H10B 10/15 comprising a resistor load element
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Abstract

An object is to provide a memory device including a memory element that can be operated without problems by a thin film transistor with a low off-state current. Provided is a memory device in which a memory element including at least one thin film transistor that includes an oxide semiconductor layer is arranged as a matrix. The thin film transistor including an oxide semiconductor layer has a high field effect mobility and low off-state current, and thus can be operated favorably without problems. In addition, the power consumption can be reduced. Such a memory device is particularly effective in the case where the thin film transistor including an oxide semiconductor layer is provided in a pixel of a display device because the memory device and the pixel can be formed over one substrate.

Claims

1. A semiconductor device comprising:

a first wiring, a second wiring, a third wiring, a fourth wiring and a fifth wiring;

a first transistor, a second transistor, a third transistor and a fourth transistor; and

a first capacitor, a second capacitor, a third capacitor and a fourth capacitor,

wherein the first wiring is electrically connected to a gate of the first transistor and a gate of the second transistor,

wherein the second wiring is electrically connected to a gate of the third transistor and a gate of the fourth transistor,

wherein the third wiring is electrically connected to one of a source and a drain of the first transistor and one of a source and a drain of the third transistor,

wherein the fourth wiring is electrically connected to one of a source and a drain of the second transistor and one of a source and a drain of the fourth transistor,

wherein the other of the source and the drain of the first transistor is electrically connected to one of electrodes of the first capacitor,

wherein the other of the source and the drain of the second transistor is electrically connected to one of electrodes of the second capacitor,

wherein the other of the source and the drain of the third transistor is electrically connected to one of electrodes of the third capacitor,

wherein the other of the source and the drain of the fourth transistor is electrically connected to one of electrodes of the fourth capacitor,

wherein each of the other of the electrodes of the first capacitor, the other of the electrodes of the second capacitor, the other of the electrodes of the third capacitor and the other of the electrodes of the fourth capacitor is electrically connected to the fifth wiring,

wherein each of the first transistor, the second transistor, the third transistor and the fourth transistor comprises an oxide semiconductor layer including a channel formation region and comprising oxygen, indium, zinc and a metal other than indium and zinc,

wherein a value of off-state current through the oxide semiconductor layer of each of the first transistor, the second transistor, the third transistor and the fourth transistor is less than or equal to 1×

10<sup>−

17</sup> A/μ

m when a channel length is 3 μ

m, voltage between the source and the drain is 1V and gate voltage is in a range of −

5V to −

20V.

2. The semiconductor device according to claim 1, wherein a hydrogen concentration in the oxide semiconductor layer of each of the first transistor, the second transistor, the third transistor and the fourth transistor is less than or equal to 5×

10¹⁹ cm<sup>−

3</sup>.

3. The semiconductor device according to claim 1, wherein a carrier concentration in the oxide semiconductor layer of each of the first transistor, the second transistor, the third transistor and the fourth transistor is less than or equal to 5×

10¹⁴ cm<sup>−

3</sup>.

4. The semiconductor device according to claim 1, wherein the oxide semiconductor layer is a crystalline oxide semiconductor layer.

5. A semiconductor device comprising:

a first wiring, a second wiring, a third wiring, a fourth wiring and a fifth wiring;

a first transistor, a second transistor, a third transistor and a fourth transistor;

a first capacitor, a second capacitor, a third capacitor and a fourth capacitor; and

a writing and refresh circuit,

wherein the first wiring is electrically connected to a gate of the first transistor and a gate of the second transistor,

wherein the second wiring is electrically connected to a gate of the third transistor and a gate of the fourth transistor,

wherein the third wiring is electrically connected to one of a source and a drain of the first transistor and one of a source and a drain of the third transistor,

wherein the fourth wiring is electrically connected to one of a source and a drain of the second transistor and one of a source and a drain of the fourth transistor,

wherein the third wiring and the fourth wiring is electrically connected to the writing and refresh circuit,

wherein the other of the source and the drain of the first transistor is electrically connected to one of electrodes of the first capacitor,

wherein the other of the source and the drain of the second transistor is electrically connected to one of electrodes of the second capacitor,

wherein the other of the source and the drain of the third transistor is electrically connected to one of electrodes of the third capacitor,

wherein the other of the source and the drain of the fourth transistor is electrically connected to one of electrodes of the fourth capacitor,

wherein each of the other of the electrodes of the first capacitor, the other of the electrodes of the second capacitor, the other of the electrodes of the third capacitor and the other of the electrodes of the fourth capacitor is electrically connected to the fifth wiring,

wherein each of the first transistor, the second transistor, the third transistor and the fourth transistor comprises an oxide semiconductor layer including a channel formation region and comprising oxygen, indium, zinc and a metal other than indium and zinc,

wherein a value of off-state current through the oxide semiconductor layer of each of the first transistor, the second transistor, the third transistor and the fourth transistor is less than or equal to 1×

10<sup>−

17</sup> A/μ

m when a channel length is 3 μ

m, voltage between the source and the drain is 1V and gate voltage is in a range of −

5V to −

20V.

6. The semiconductor device according to claim 5, wherein a hydrogen concentration in the oxide semiconductor layer of each of the first transistor, the second transistor, the third transistor and the fourth transistor is less than or equal to 5×

10¹⁹ cm<sup>−

3</sup>.

7. The semiconductor device according to claim 5, wherein a carrier concentration in the oxide semiconductor layer of each of the first transistor, the second transistor, the third transistor and the fourth transistor is less than or equal to 5×

10¹⁴ cm<sup>−

3</sup>.

8. The semiconductor device according to claim 5, wherein the oxide semiconductor layer is a crystalline oxide semiconductor layer.