Selection device

• US 9,735,796 B2
• Filed: 10/15/2015
• Issued: 08/15/2017
• Est. Priority Date: 12/09/2009
• Status: Active Grant

• Current Assignee: Trigence Semiconductor, Inc.
• Original Assignee: Trigence Semiconductor, Inc.
• Inventors: Yasuda, Akira, Okamura, Jun-ichi
• Primary Examiner(s): Jerez Lora, William A
• Application Number:
  US14/884,155
• Publication Number:
  US 20160036459A1
• Time in Patent Office: 670 Days
• Field of Search: 381111, 381116, 381117, 381 81, 381 85, 381123, 381120, 341144, 341118, 341120, 341153
• CPC Class Codes: H03M 1/066 by continuously permuting the elements used, i.e. dynamic element matching
• CPC Class Codes: H03M 1/74 Simultaneous conversion
• CPC Class Codes: H03M 3/502 Details of the final digital/analogue conversion following the digital delta-sigma modulation
• CPC Class Codes: H04R 2420/03 Connection circuits to selectively connect loudspeakers or headphones to amplifiers
• CPC Class Codes: H04R 3/00 Circuits for transducers , loudspeakers or microphones

Abstract

Provided is a selection device including an acquisition section for acquiring digital selection signals, and an output section for outputting selection signals to respective unit cells, each unit cell capable of being commanded to output the value zero. The selection device is characterized in that: each selection signal is for commanding the unit cell to output a value corresponding to that selection signal; the sum of the values to be output as commanded by the respective selection signals, which are output to the respective unit cells, is a value determined in association with the digital selection signal; and if the output corresponding to the digital selection signal is the value zero, then selection signals each commanding to output a non-zero value (N) are output to some of the unit cells.

Claims

1. A selection device receiving a digital signals and outputting a total value of outputs of a plurality of unit cells being a drive circuit which drives a voice coil, each of the unit cells outputting a plus value and a minus value, comprising:

a circuit outputting a signal representing a number of unit cells outputting a plus value among the plurality of unit cells, and a signal representing a number of unit cells outputting a minus value among the plurality of unit cells;

a selection circuit of a plus side selecting a unit cell outputting a plus value among the plurality of unit cells based on a frequency of selection of the unit cell, wherein a number of unit cells outputting a plus value and selected by the selection circuit of a plus side is determined by the signal representing a number of unit cells outputting a plus value among the plurality of unit cells,

a selection circuit of a minus side selecting a unit cell outputting a minus value from the plurality of unit cells based on a frequency of selection of the unit cell, wherein a number of unit cells outputting a minus value and selected by the selection circuit of a minus side determined by the signal representing a number of cells outputting a minus value among the plurality of unit cells,

wherein, taking the average in time of the summation of the plus value unit cell and the minus value unit cell will represent the digital signal value.

2. The selection device according to claim 1, wherein each of the selection circuit of a plus side and the selection circuit of a minus side perform the selection of the unit cells in an ascending order of the frequency of selection of the unit cell selected by each of the selection circuit of a plus side and the selection circuit of a minus side.

3. The selection device according to claim 2 further includes a first integration part calculating the frequency of selection of the unit cell selected by each of the selection circuit of a plus side and the selection circuit of a minus side,

wherein each of the selection circuit of a plus side and the selection circuit of a minus side perform the selection of unit cells in an ascending order of the frequency of selection of the unit cell selected by each of the selection circuit of a plus side and the selection circuit of a minus side based on the outputs of the first integration part.

4. The selection device according to claim 1, wherein each of the selection circuit of a plus side and the selection circuit of a minus side outputs a selection signal to the selected unit cell,

and further includes,

a first adder input the selection signal, each of the selection circuit of a plus side and the selection circuit of a minus side outputs the selection signal,

a second integration part input the outputs of the first adder,

wherein, each of the selection circuit of a plus side and the selection circuit of a minus side perform the selection of the unit cells based on the outputs of the second integration part.

5. The selection device according to claim 4, further includes a first sort circuit input the outputs of the second integration part,

wherein, each of the selection circuit of a plus side and the selection circuit of a minus side perform the selection of the unit cells in an ascending order of the frequency of selection of the selected unit cell by the outputs of the first sort circuit.

6. The selection device according to claim 4, wherein the second integration part is configured by a plurality of integration circuits.

7. The selection device according to claim 1, wherein each of the selection circuit of a plus side and the selection circuit of a minus side outputs a selection signal to the selected unit cell,

and further includes,

a second adder and a third adder input the selection signal, each of the selection circuit of a plus side and the selection circuit of a minus side outputs the selection signal, wherein a weighting by an addition coefficient is different between the second adder and the third adder,

a third integration part input the outputs of the second adder,

a fourth integration part input the outputs of the third adder,

wherein, the selection circuit of a plus side performs the selection of the unit cells based on the outputs of the third integration part, and the selection circuit of a minus side performs the selection of the unit cells based on the outputs of the fourth integration part.

8. The selection device according to claim 7, further includes,

a second sort circuit input the outputs of the third integration part,

a third sort circuit input the outputs of the fourth integration part,

wherein, each of the selection circuit of a plus side and the selection circuit of a minus side performs the selection of unit cells in an ascending order of the frequency of selection of the unit cell selected by each of the selection circuit of a plus side and the selection circuit of a minus side based on the outputs of each of the second sort circuit and the third sort circuit.