Charge transfer circuit with storage nodes in image sensors

• US 9,741,754 B2
• Filed: 03/06/2013
• Issued: 08/22/2017
• Est. Priority Date: 03/06/2013
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Li, Xiangli, Fan, Xiaofeng, Wan, Chung Chun
• Primary Examiner(s): Luu, Thanh
• Assistant Examiner(s): Bennett, Jennifer
• Application Number:
  US13/787,094
• Publication Number:
  US 20140252201A1
• Time in Patent Office: 1,630 Days
• Field of Search: 2502081, 250214 R, 2502141, 257257, 257258, 257290, 257291, 257292, 257431, 257443, 257445, 348296, 348294, 348302, 348299, 348298, 348297, 348314
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14616 characterised by the channel of the transistor, e.g. channel having a doping gradient
• CPC Class Codes: H04N 25/587 acquired sequentially, e.g. using the combination of odd and even image fields
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/771 comprising storage means other than floating diffusion
• CPC Class Codes: H04N 25/79 Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors

Abstract

Apparatuses and methods for charge transfer in image sensors are disclosed. One example of an image sensor pixel may include a first charge storage node and a second charge storage node. A transfer circuit may be coupled between the first and second charge storage nodes, and the transfer circuit may have a first region proximate the first charge storage node and configured to have a first potential. The transfer circuit may also have a second region proximate the second charge storage node configured to have a second, higher potential. An input node may be configured to control the first and second potentials based on a transfer signal provided to the input node.

Claims

1. An image sensor pixel, comprising:

a photodiode;

a first charge storage node;

a first transfer gate between the photodiode and the first charge storage node and configured to transfer charge from the photodiode to the first charge storage node;

a second charge storage node;

a second transfer gate between the first charge storage node and the second charge storage node and configured to transfer charge from the first charge storage node to the second charge storage node;

a third charge storage node; and

a third transfer gate between the second charge storage node and the third charge storage node and configured to transfer charge from the second charge storage node to the third charge storage node;

wherein the second transfer gate comprises a transfer circuit gate that is included in a transfer circuit, the transfer circuit comprising;

a first region under a portion of the transfer circuit gate proximate the first charge storage node and configured to have a first variable potential;

a second region laterally offset from the first region under a remaining portion of the transfer circuit gate and configured to have a second variable potential, the second region extending away from the first region and beyond the transfer circuit gate to the second charge storage node; and

a pinning layer over the second charge storage node and over a portion of the second region not under the transfer circuit gate, the pinning layer and the portion of the second region not under the transfer circuit gate forming a barrier between the second region under the transfer circuit gate and the second charge storage node, wherein

the transfer circuit gate is configured to control the first and the second variable potentials based on a transfer signal provided to the transfer gate.

2. The image sensor pixel of claim 1, wherein

the first charge storage node, the second charge storage node, and the second region are comprised of a first dopant type;

and

the first region and the pinning layer are comprised of a second dopant type.

3. The image sensor pixel of claim 1, wherein the third charge storage node comprises a floating diffusion node.

4. The image sensor pixel of claim 1, wherein the image sensor comprises a stacked CMOS image sensor, with the photodiode on a first semiconductor chip and transfer circuitry on a second semiconductor chip stacked together with the first semiconductor chip, further wherein the first charge storage node is a stack contact on the second semiconductor chip and the second charge storage node is a global shutter storage node on the second semiconductor chip.

5. The image sensor pixel of claim 1, wherein the first charge storage node is configured to have a third potential and the second charge storage node is configured to have a fourth potential and the third and fourth potentials are substantially the same.

6. The image sensor pixel of claim 1, wherein the first charge storage node is configured to have a third potential and the second charge storage node is configured to have a fourth potential and the third potential is greater than the fourth potential.

7. The image sensor pixel of claim 1, wherein the first charge storage node is configured to have a third potential and the second charge storage node is configured to have a fourth potential and the fourth potential is greater than the third potential.

8. The image sensor pixel of claim 2, the first charge storage node is configured to have a first fixed potential, the second charge storage node is configured to have a second fixed potential, and the barrier is configured to have a third fixed potential.

9. The image sensor pixel of claim 1, further comprising an anti-blooming gate operably connected to the first charge storage node.

10. An integrated circuit, comprising:

a photodiode;

a first node comprising a first dopant type operatively coupled to the photodiode and configured to store charge;

a second node comprising the first dopant type operatively coupled to the first node and configured to receive charge from the first node; and

a transfer circuit coupling the first node to the second node, the transfer circuit comprising;

a transfer gate positioned between the first and the second nodes;

a barrier region comprising a second dopant type under a portion of the transfer gate proximate the first node, the barrier region having a first variable potential configured to be controlled by a transfer signal applied to the transfer gate;

a storage region comprising the first dopant type laterally offset from the barrier region under a remaining portion of the transfer gate and having a second variable potential configured to be controlled by the transfer signal applied to the transfer gate, the storage region extending away from the barrier region beyond the transfer gate to the second node; and

a pinning layer formed over the second node and a portion of the storage region not under the transfer gate, the pinning layer and the portion of the storage region not under the transfer gate forming a barrier between the portion of the storage region under the transfer gate and the second node, wherein

the second variable potential is higher than the first variable potential.

11. The integrated circuit of claim 10, wherein the transfer circuit is a modified field effect transistor.

12. The integrated circuit of claim 10, wherein a relative difference between the first and the second variable potentials is constant across a plurality of different transfer signal voltages.

13. The integrated circuit of claim 10, further comprising an anti-blooming gate operably connected to the first node.

14. An image sensor pixel, comprising:

a photodiode;

a first charge storage node comprising a first dopant type and operatively connected to the photodiode;

a second charge storage node comprising the first dopant type operatively connected to the first charge storage node through a transfer circuit positioned between the first and the second charge storage nodes, the transfer circuit comprising;

a transfer gate;

a first region comprising a second dopant type positioned below a portion of the transfer gate proximate the first charge storage node; and

a second region comprising the first dopant type between the first region and the second charge storage node, wherein a first portion of the second region is positioned below a remaining portion of the transfer gate and a second portion of the second region extends beyond the transfer gate to the second charge storage node; and

a pinning layer comprising the second dopant type positioned over the second charge storage node and the second portion of the second region,

wherein a dopant concentration of the second region is less than a dopant concentration of the second charge storage node.

15. The image sensor pixel of claim 14, wherein a dopant concentration of the pinning layer is greater than a dopant concentration of the first region.

16. The image sensor pixel of claim 14, wherein the second charge storage node comprises a floating diffusion node.

17. The image sensor pixel of claim 14, wherein the transfer gate is configured to control a first potential of the first region and a second potential of the first portion of the second region based on a transfer signal provided to the transfer gate.

18. The image sensor pixel of claim 14, wherein the first region and the second region are laterally offset from one another such that the first and the second regions do not overlap in depth below the transfer gate.

19. The image sensor pixel of claim 14, further comprising an anti-blooming gate operably connected to the first charge storage node.