Chip to wafer package with top electrodes and method of forming

• US 9,748,162 B2
• Filed: 01/06/2015
• Issued: 08/29/2017
• Est. Priority Date: 01/16/2014
• Status: Active Grant

• Current Assignee: China Wafer Level CSP Co., Ltd.
• Original Assignee: China Wafer Level CSP Co., Ltd.
• Inventors: Wang, Zhiqi, Li, Junjie, Yang, Ying, Yu, Qiong, Wang, Wei
• Primary Examiner(s): Schoenholtz, Joseph
• Application Number:
  US14/590,891
• Publication Number:
  US 20150200153A1
• Time in Patent Office: 966 Days
• Field of Search: None
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/24146 the HDI interconnect connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/73217 Layer and HDI connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/82039 using a laser
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/92144 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/92244 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06568 : the devices decreasing in size, e.g. pyramidical stack
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/071 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER

Abstract

A chip package and a method for forming the same are provided. The method includes: providing a first chip, wherein the first chip comprises a first surface and a second surface, and a first plurality of pads are disposed on the first surface; providing a second chip, wherein the second chip comprises a third surface and a fourth surface, a second plurality of pads are disposed on the third surface; combining the second surface of the first chip and the third surface of the second chip, wherein the second plurality of pads are out of the combination area of the first chip and the second chip; and forming a first insulation layer, wherein the first insulation layer covers the first chip, and is combined with the second chip. Processes of the method are simple, and the chip package is small.

Claims

1. A method for forming a chip package, comprising:

providing a first chip, wherein the first chip comprises a first surface and a second surface opposite to the first surface, and a first plurality of pads are disposed on the first surface of the first chip;

providing a second chip, wherein the second chip comprises a third surface and a fourth surface opposite to the third surface, a second plurality of pads are disposed on the third surface of the second chip, and the area of the second chip is larger than the area of the first chip;

combining the second surface of the first chip and the third surface of the second chip, wherein the second plurality of pads are out of a combination area of the first chip and the second chip; and

forming a first insulation layer, wherein the first insulation layer covers the first chip, and is combined with the second chip, and wherein the first insulation layer covers the first plurality of pads and the second plurality of pads;

etching the first insulation layer to form a first plurality of openings exposing the first plurality of pads, and a second plurality of openings exposing the second plurality of pads;

forming a plurality of metal interconnection structures by applying a metal material on bottoms and sidewalls of the first openings and the second openings, and a top surface of the first insulation layer, forming a metal material layer and selectively removing the metal material layer, wherein one or more of the first plurality of pads are electrically connected to one or more of the second plurality of pads through the metal interconnection structures; and

forming a second insulation layer on the first insulation layer and the plurality of metal interconnection structures, wherein at least part of the second insulation layer is filled in the first openings and the second openings.

2. The method according to claim 1, wherein the second surface of the first chip and the third surface of the second chip are combined through an insulation adhesive layer.

3. The method according to claim 2, wherein a sum of the combination area between the first insulation layer and the second chip and the combination area between the insulation adhesive layer and the second chip is larger than the area of the first chip.

4. The method according to claim 1, wherein the first insulation layer comprises a photosensitive dry film, a non-photosensitive dry film or a molding material.

5. The method according to claim 1, wherein the plurality of metal interconnection structures cover bottoms and sidewalls of the first plurality of openings and the second plurality of openings, and parts of the top surface of the first insulation layer, so that the plurality of metal interconnection structures are electrically connected with the first plurality of pads and the second plurality of pads.

6. The method according to claim 1, wherein the second insulation layer has a third plurality of openings exposing parts of the plurality of metal interconnection structures;

and

the method further comprises;

forming a plurality of metal pillars in the third plurality of openings, wherein the plurality of metal pillars are electrically connected with the plurality of metal interconnection structures, and are higher than the top surface of the second insulation layer.

7. The method according to claim 1, wherein the second chip is a part of a wafer, and after forming the plurality of metal pillars, the method further comprises:

cutting the wafer to form a package structure comprising the first chip and the second chip.

8. The method according to claim 1, wherein a number of the first chip is one or more, a number of the second chip is one or more, the second surfaces of the one or more first chips are combined with the third surfaces of the one or more second chips, and the first plurality of pads of the one or more first chips are electrically connected with the second plurality of pads of the one or more second chips through the plurality of metal interconnection structures, or a number of the first plurality pads of more than one first chip are connected through the plurality of metal interconnection structures, or a number of the second plurality pads of more than one second chip are connected through the plurality of metal interconnection structures.

9. A chip package, comprising:

a first chip, wherein the first chip comprises a first surface and a second surface opposite to the first surface, and a first plurality of pads are disposed on the first surface the first chip;

a second chip, wherein the second chip comprises a third surface and a fourth surface opposite to the third surface, a second plurality of pads are disposed on the third surface of the second chip, the area of the second chip is larger than the area of the first chip, the second surface of the first chip is combined with the third surface of the second chip, and the second plurality of pads are out of a combination area of the first chip and the second chip; and

a first insulation layer, wherein the first insulation layer covers the first chip and is combined with the second chip, and wherein the first insulation layer covers the first plurality of pads and the second plurality of pads, the first insulation layer has a first plurality of openings exposing the first plurality of pads and a second plurality of openings exposing the second plurality of pads;

a plurality of metal interconnection structures formed on the first pads, the second pads and a top surface of the first insulation layer by applying a metal material on bottoms and sidewalls of the first openings and the second openings, and a top surface of the first insulation layer, forming a metal material layer, and selectively removing the metal material layer, wherein one or more of the first plurality of pads are electrically connected to one or more of the second plurality of pads through the metal interconnection structures; and

a second insulation layer, wherein the second insulation layer is disposed on the first insulation layer and the plurality of metal interconnection structures, and at least part of the second insulation layer is filled in the first openings and the second openings.

10. The chip package according to claim 9, further comprising:

an insulation adhesive layer, disposed between the second surface of the first chip and the third surface of the second chip.

11. The chip package according to claim 10, wherein a sum of the combination area between the first insulation layer and the second chip and the combination area between the insulation adhesive layer and the second chip is larger than the area of the first chip.

12. The chip package according to claim 9, wherein the first insulation layer is a photosensitive dry film, a non-photosensitive dry film or a molding material.

13. The chip package according to claim 9, wherein the plurality of metal interconnection structures cover bottoms and sidewalls of the first plurality of openings and the second plurality of openings, and parts of the top surface of the first insulation layer, so that the plurality of metal interconnection structures are electrically connected with the first plurality of pads and the second plurality of pads.

14. The chip package according to claim 9, wherein

the second insulation layer has a third plurality of openings exposing parts of the plurality of metal interconnection structures;

and

the chip package further comprises;

a plurality of metal pillars, wherein the plurality of metal pillars are disposed in the third plurality of openings, and are higher than the top surface of the second insulation layer.

15. The chip package according to claim 9, wherein a number of the first chip is one or more, a number of the second chip is one or more, the second surfaces of the one or more first chips are combined with the third surfaces of the one or more second chips, and the first plurality of pads of the one or more first chips are electrically connected with the second plurality of pads of the one or more second chips through the plurality of metal interconnection structures, or a number of the first plurality pads of more than one first chip are connected through the plurality of metal interconnection structures, or a number of the second plurality pads of more than one second chip are connected through the plurality of metal interconnection structures.