Method of forming a semiconductor device structure and semiconductor device structure

• US 9,748,259 B1
• Filed: 02/25/2016
• Issued: 08/29/2017
• Est. Priority Date: 02/25/2016
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Faul, Juergen, Jakubowski, Frank
• Primary Examiner(s): Patel, Reema
• Assistant Examiner(s): Christopher, Steven
• Application Number:
  US15/053,485
• Publication Number:
  US 20170250191A1
• Time in Patent Office: 551 Days
• Field of Search: None
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 28/00 Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/42352 with the gate at least partly formed in a trench
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/30 characterised by the memory core region

Abstract

The present disclosure provides, in accordance with some illustrative embodiments, a semiconductor device structure including a hybrid substrate comprising an SOI region and a bulk region, the SOI region comprising an active semiconductor layer, a substrate material, and a buried insulating material interposed between the active semiconductor layer and the substrate material, and the bulk region being provided by the substrate material, an insulating structure formed in the hybrid substrate, the insulating structure separating the bulk region and the SOI region, and a gate electrode formed in the bulk region, wherein the insulating structure is in contact with two opposing sidewalls of the gate electrode.

Claims

1. A method of forming a semiconductor device structure, the method comprising:

providing an SOI substrate comprising a substrate material, an active semiconductor layer positioned above said substrate material, and a buried insulating material interposed between said active semiconductor layer and said substrate material;

forming an insulating structure in said SOI substrate, said insulating structure laterally separating a first substrate portion of said substrate material from two adjacent SOI substrate portions;

after forming said insulating structure, forming a recess in said first substrate portion, a bottom of said recess exposing an upper surface portion of said substrate material;

applying an etching process to said recess, said etching process being unselective with regard to said insulating structure and said substrate material; and

after applying an etching process to said recess, forming a gate electrode inside of said recess and above said upper surface portion of said substrate material at said bottom of said recess.

2. The method of claim 1, further comprising forming one of a SONOS structure, MONOS structure, and a floating gate structure inside of said recess and above said exposed upper surface portion of said substrate material prior to forming said gate electrode.

3. The method of claim 1, further comprising forming a masking pattern over said first substrate portion and said recess prior to applying said etching process, wherein said substrate material and said insulating structure are unselectively etched in said etching process.

4. The method of claim 3, wherein, during said etching process, said substrate material in said first substrate portion is partially etched back relative to substrate material covered by said masking pattern.

5. The method of claim 1, wherein said insulating structure is partially etched back in said etching process, said etched back insulating structure having a recessed portion adjacent to said substrate material in said first substrate portion.

6. The method of claim 3, further comprising forming a PC masking pattern on said substrate region in alignment with said masking pattern, said PC masking pattern leaving surface regions of said first substrate region adjacent to an upper surface of said gate electrode exposed to further processing.

7. The method of claim 1, wherein said etching process comprises one of a plasma etching process and a reactive ion etch process.

8. The method of claim 1, further comprising forming a first oxide layer on said exposed upper surface portion of said substrate material in said recess and subsequently forming one of a nitride material and a floating gate material on said first oxide layer.

9. The method of claim 8, further comprising forming a second oxide layer on said one of said nitride material and said floating gate material, and subsequently forming said gate electrode.

10. The method of claim 9, wherein forming said gate electrode comprises depositing a gate electrode material over said first substrate region and subsequently leveling said deposited gate electrode material with said adjacent SOI substrate portions.

11. The method of claim 6, wherein said PC masking pattern represents a negative to said masking pattern in said first substrate region.

12. The method of claim 6, further comprising forming a sidewall spacer structure to said gate electrode and subsequently forming at least one of a halo, source/drain extension and deep source/drain implantation region in said substrate material of said first substrate portion.

13. The method of claim 12, further comprising subsequently forming semiconductor devices in and over said adjacent SOI regions.

14. The method of claim 1, wherein forming said recess in said first substrate portion comprises recessing a portion of said insulating structure.

15. The method of claim 1, further comprising, after forming said gate electrode, forming source/drain regions in said substrate material of said first substrate portion.

16. A method of forming a semiconductor device structure, the method comprising:

providing an SOI substrate comprising a substrate material, an active semiconductor layer positioned above said substrate material, and a buried insulating material interposed between said active semiconductor layer and said substrate material;

forming an insulating structure in said SOI substrate, said insulating structure laterally separating a first substrate portion of said substrate material from two adjacent SOI substrate portions;

after forming said insulating structure, forming a recess in said first substrate portion, a bottom of said recess exposing an upper surface portion of said substrate material;

forming one of a SONOS structure and a floating gate inside of said recess and above said exposed upper surface portion of said substrate material at said bottom of said recess; and

forming a gate electrode inside of said recess and above said one of said SONOS structure and said floating gate.

17. The method of claim 16, wherein forming said recess in said first substrate portion comprises recessing a portion of said insulating structure.

18. The method of claim 16, further comprising, after forming said gate electrode, forming source/drain regions in said substrate material of said first substrate portion.

19. A method of forming a semiconductor device structure, the method comprising:

providing an SOI substrate comprising an active semiconductor layer, a substrate material, and a buried insulating material interposed between said active semiconductor layer and said substrate material;

forming an insulating structure in said SOI substrate, said insulating structure laterally separating a first substrate portion from two adjacent SOI substrate portions;

forming a recess in said first substrate portion, said recess exposing an upper surface portion of said substrate material;

forming a first oxide layer on said exposed upper surface portion of said substrate material in said recess;

forming one of a nitride material and a floating gate material on said first oxide layer;

forming a second oxide layer on said one of said nitride material and said floating gate material; and

forming a gate electrode in said recess above said second oxide layer.