Battery cell monitoring circuit and battery cell monitoring system

• US 9,753,089 B2
• Filed: 03/08/2013
• Issued: 09/05/2017
• Est. Priority Date: 03/26/2012
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Suzuki, Atsuhisa
• Primary Examiner(s): Rodas, Richard Isla
• Assistant Examiner(s): Bui, Dung V
• Application Number:
  US13/791,393
• Publication Number:
  US 20130261815A1
• Time in Patent Office: 1,642 Days
• Field of Search: 320116, 700286, 702 63
• CPC Class Codes: G01R 31/3648 comprising digital calculation means, e.g. for performing an algorithm
• CPC Class Codes: G01R 31/382 Arrangements for monitoring battery or accumulator variables, e.g. SoC
• CPC Class Codes: G01R 31/396 Acquisition or processing of data for testing or for monitoring individual cells or groups of cells within a battery
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/263 Arrangements for using multiple switchable power supplies, e.g. battery and AC G06F1/30 takes precedence
• CPC Class Codes: G06F 1/3212 Monitoring battery levels, e.g. power saving mode being initiated when battery voltage goes below a certain level
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A battery cell monitoring system includes multiple battery monitoring circuits, each connected to a corresponding battery cell, and a microcomputer for controlling the monitoring circuits. The battery monitoring circuits include a data output circuit that outputs a data signal corresponding to the monitoring results for the battery cell monitored thereby and a multiplexer that outputs either the monitoring results received from the data output circuit or monitoring results received from another battery monitoring circuit. The battery cell monitoring circuit includes a flip-flop circuit receiving a clock signal and the signal output from the multiplexer which is latched in synchronization with the clock signal.

Claims

1. A battery cell monitoring system, comprising:

a plurality of battery cell monitoring circuits for monitoring battery cells connected in series; and

a microcomputer that outputs an address signal containing address information designating one or more of the battery cell monitoring circuits for generating a data signal and a clock signal;

wherein each battery cell monitoring circuit of the plurality comprises;

an address input terminal for input of the address signal;

an address output terminal for output of the address signal;

a clock input terminal for input of the clock signal;

a clock output terminal for output of the clock signal;

a data output circuit for output of a data signal corresponding to a battery cell monitoring result;

a data input terminal for input of the data signal from another battery monitoring circuit;

a data output terminal;

a multiplexer having an input terminal connected to the data input terminal and the data output circuit, wherein the multiplexer is configured to receive data signals through the data input terminal and from the data output circuit and to output the data signal received from the data output circuit when the battery cell monitoring circuit is the designated battery cell monitoring circuit and to output the data signal received through the data input terminal otherwise; and

a flip-flop circuit having a clock input terminal for receiving the clock signal and a data terminal for receiving the data signal from the multiplexer, wherein the flip-flop circuit latches the data signal from the multiplexer in synchronization with the clock signal, and the latched data signal is output to the data output terminal.

2. The battery cell monitoring system according to claim 1, wherein

the plurality of battery monitoring circuits includes a first battery cell monitoring circuit and a second battery cell monitoring circuit,

the first battery cell monitoring circuit having the address input terminal, the clock input terminal, and the data output terminal connected to the microcomputer without another battery cell monitoring circuit connected between the first battery cell monitoring circuit and the microcomputer, and

the second battery cell monitoring circuit having the address input terminal, the clock input terminal, and the data output terminal connected to the address output terminal, the clock output terminal, and the data input terminal of the first battery cell monitoring circuit, respectively.

3. The battery cell monitoring system according to claim 2, wherein the address input terminal and the data output terminal are implemented as an input-output terminal that is configured to switch between operating as the address input terminal and operating as the data output terminal.

4. The battery cell monitoring system according to claim 3, wherein connections between the first battery cell monitoring circuit and the microcomputer each include an insulating coupler.

5. The battery cell monitoring system according to claim 1, further comprising:

a last battery monitoring circuit connected to one of the plurality of battery monitoring circuits, the last battery monitoring circuit having an address input terminal, a clock input terminal, and a data output terminal connected to the address output terminal, the clock output terminal, and the data input terminal of the one of the plurality of battery cell monitoring circuit, respectively.

6. The battery cell monitoring system according to claim 5, wherein the last battery monitoring circuit does not include an address output terminal, a clock output terminal, and a data input terminal.

7. The battery cell monitoring system according to claim 1, wherein one battery cell monitoring circuit of the plurality has nothing connected to the address output terminal, the clock output terminal, and the data input terminal.

8. The battery cell monitoring system according to claim 1, the battery monitoring circuits each further comprising:

an address input buffer connected between the address input terminal and an input of the data output circuit;

an address output buffer connected between an output of the address input buffer and the address output terminal;

a clock input buffer connected between the clock input terminal and the clock terminal of the flip-flop circuit;

a clock output buffer connected between an output of the clock input buffer and the clock output terminal;

a data input buffer connected between the data input terminal and an input of the multiplexer; and

a data output buffer connected between an output of the flip-flop circuit and the data output terminal.

9. The battery cell monitoring system according to claim 8, wherein a transfer delay time of the address signal from the address input terminal to the address output terminal of the battery cell monitoring circuit is configured to be equal to a transfer delay time of the clock signal from the clock input terminal to the clock output terminal.

10. The battery cell monitoring system according to claim 1, wherein on the basis of a delay time of the clock signal from the microcomputer to the assigned selected battery cell monitoring circuit and a transfer time of the data signal from the selected battery cell monitoring circuit to the microcomputer, the selected battery cell monitoring circuit is configured to control a timing of the output of the data signal so that head positions of data signals output from the battery cell monitoring circuits are approximately the same.

11. The battery cell monitoring system according to claim 1, wherein communication between the microcomputer and the plurality of battery cell monitoring circuits is synchronous with the clock signal.

12. A monitoring circuit for a battery cell, comprising:

an address input terminal for input of an address signal designating a selected battery cell monitoring circuit;

an address output terminal for output of the address signal;

a clock input terminal for input of a clock signal;

a clock output terminal for output of the clock signal;

a data output circuit configured to output a data signal corresponding to a monitoring result for the battery cell;

a data input terminal for input of data signals from other battery cell monitoring circuits;

a data output terminal;

a multiplexer having an input terminal connected to the data input terminal and the data output circuit, wherein the multiplexer is configured receive data signals through the data input terminal and from the data output circuit and to output the data signal received from the data output circuit when the monitoring circuit is selected and to output the data signal received through the data input terminal otherwise; and

a flip-flop circuit having a clock input terminal for receiving the clock signal and a data terminal for receiving the data signal from the multiplexer, wherein the flip-flop circuit latches the data signal from the multiplexer in synchronization with the clock signal, and the latched data signal is output to the data output terminal.

13. The monitoring circuit according to claim 12, wherein the address input terminal and the data output terminal are implemented as an input-output terminal that is configured to switch between operating as the address input terminal and operating as the data output terminal.

14. The monitoring circuit according to claim 13, further comprising:

an address input buffer connected between the address input terminal and an input of the data output circuit;

an address output buffer connected between an output of the address input buffer and the address output terminal;

a clock input buffer connected between the clock input terminal and the clock terminal of the flip-flop circuit;

a clock output buffer connected between an output of the clock input buffer and the clock output terminal;

a data input buffer connected between the data input terminal and an input of the multiplexer, and

a data output buffer connected between an output of the flip-flop circuit and the data output terminal.

15. The monitoring circuit according to claim 13, wherein the address input terminal, the clock signal input terminal, and the data output terminal are connected to a microcomputer providing the address signal and the clock signal.

16. The monitoring circuit according to claim 15, wherein on the basis of a delay time of the clock signal from the microcomputer to the battery cell monitoring circuit and a transfer time of the data signal from the battery cell monitoring circuit to the microcomputer, the battery cell monitoring circuit is configured to control a timing of the output of the data signal.