Microcontroller programmable system on a chip with programmable interconnect

• US 9,766,650 B2
• Filed: 09/25/2015
• Issued: 09/19/2017
• Est. Priority Date: 10/26/2000
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Snyder, Warren S
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US14/866,439
• Publication Number:
  US 20160019169A1
• Time in Patent Office: 725 Days
• Field of Search: None
• CPC Class Codes: G05B 19/0423 Input/output
• CPC Class Codes: G05B 2219/25033 structure, control, syncronization, data, alarm, connect I-O line to interface
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 13/102 where the programme performs an interfacing function, e.g. device driver G06F13/105 takes precedence; scheduling within device drivers G06F9/52; contention policies within device drivers G06F9/4881
• CPC Class Codes: G06F 13/36 for access to common bus or bus system
• CPC Class Codes: G06F 13/40 Bus structure for computer networks G06F15/163; for optical bus networks H04B10/25
• CPC Class Codes: G06F 13/4068 Electrical coupling
• CPC Class Codes: G06F 13/4282 on a serial bus, e.g. I2C bus, SPI bus on daisy chain buses G06F13/4247
• CPC Class Codes: G06F 15/7817 Specially adapted for signal processing, e.g. Harvard architectures
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 9/44505 Configuring for program initiating, e.g. using registry, configuration files
• CPC Class Codes: G06G 7/06 Programming arrangements, e.g. plugboard for interconnecting functional units of the computer; Digital programming hybrid computers G06J
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: H03B 5/32 being a piezoelectric resonator selection of piezoelectric material H10N30/00
• CPC Class Codes: H03B 5/364 the amplifier comprising field effect transistors H03B5/366 takes precedence
• CPC Class Codes: H03H 19/004 Switched capacitor networks
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/014 Modifications of generator to ensure starting of oscillations
• CPC Class Codes: H03K 3/02315 Stabilisation of output, e.g. using crystal

Abstract

A programmable device includes reconfigurable analog circuitry, reconfigurable digital circuitry, a plurality of input/output (I/O) blocks, and a global mapping system. The global mapping system is configured to selectively couple the plurality of I/O blocks with analog functional units of the reconfigurable analog circuitry and with digital functional units of the reconfigurable digital circuitry.

Claims

1. A programmable device, comprising:

reconfigurable analog circuitry;

reconfigurable digital circuitry;

a plurality of input/output (I/O) blocks; and

a global mapping system configured to selectively couple the plurality of I/O blocks with analog functional units of the reconfigurable analog circuitry and with digital functional units of the reconfigurable digital circuitry.

2. The programmable device of claim 1, further comprising a system timing block configured to generate a plurality of time bases each provided to at least one of the reconfigurable analog circuitry and the reconfigurable digital circuitry.

3. The programmable device of claim 2, further comprising a programmable interconnect configured to distribute one or more of the plurality of time bases to the reconfigurable digital circuitry for implementing a universal asynchronous receiver transmitter (UART) function in the reconfigurable digital circuitry.

4. The programmable device of claim 1, wherein the global mapping system further comprises an input global mapping unit and an output global mapping unit.

5. The programmable device of claim 1, wherein each of the analog functional units comprises a parametric setting register configured to store a value representing an electrical signal characteristic.

6. The programmable device of claim 1, wherein the reconfigurable analog circuitry comprises:

one or more switched capacitor blocks; and

one or more continuous time blocks, wherein for each continuous time block of the one or more continuous time blocks, the continuous time block is configured to generate an output reflecting changes in an analog signal that varies continuously over time and that is supplied as an input to the continuous time block.

7. The programmable device of claim 1, wherein the reconfigurable analog circuitry is reconfigurable to perform any of a plurality of analog functions, wherein each of the digital functional units comprises a plurality of selectable logic circuits, and wherein each of the digital functional units is reconfigurable to perform any of a plurality of predetermined digital functions.

8. A method of operating a programmable device, comprising:

performing an analog function on an analog signal in reconfigurable analog circuitry of the programmable device;

performing a digital function on a digital signal in reconfigurable digital circuitry of the programmable device;

in a global mapping system, selectively coupling a plurality of I/O blocks of the programmable device with analog functional units of the reconfigurable analog circuitry and with digital functional units of the reconfigurable digital circuitry.

9. The method of claim 8, further comprising:

generating a plurality of time bases in a system timing block; and

providing the plurality of time bases to at least one of the reconfigurable analog circuitry and the reconfigurable digital circuitry.

10. The method of claim 9, further comprising distributing one or more of the plurality of time bases via a programmable interconnect to the reconfigurable digital circuitry for implementing a universal asynchronous receiver transmitter (UART) function in the reconfigurable digital circuitry.

11. The method of claim 8, further comprising, for each analog functional unit of the analog functional units, storing a value representing an electrical signal characteristic in a parametric setting register of the analog functional unit.

12. The method of claim 8, further comprising reconfiguring the reconfigurable analog circuitry and the reconfigurable digital circuitry by transferring an instruction from a read-only memory (ROM) to the reconfigurable analog circuitry and the reconfigurable digital circuitry.

13. The method of claim 8, further comprising, in a continuous time block of the reconfigurable analog circuitry, generating an output reflecting changes in an analog signal that varies continuously over time and that is supplied as an input to the continuous time block.

14. The method of claim 9, further comprising:

reconfiguring the reconfigurable analog circuitry to perform each of a plurality of analog functions, and

reconfiguring the reconfigurable digital circuitry to perform each of a plurality of digital functions.

15. A programmable system, comprising:

a microprocessor;

reconfigurable analog circuitry coupled with the microprocessor;

reconfigurable digital circuitry coupled with the microprocessor;

a plurality of input/output (I/O) blocks; and

a global mapping system configured to selectively couple the plurality of I/O blocks with analog functional units of the reconfigurable analog circuitry and with digital functional units of the reconfigurable digital circuitry.

16. The programmable system of claim 15, wherein the microprocessor is configured to reconfigure the reconfigurable analog circuitry and the reconfigurable digital circuitry by transferring an instruction from a read-only memory (ROM) to the reconfigurable analog circuitry and the reconfigurable digital circuitry.

17. The programmable system of claim 15, further comprising a system timing block configured to generate a plurality of time bases provided to at least one of the reconfigurable analog circuitry and the reconfigurable digital circuitry.

18. The programmable system of claim 15, wherein the global mapping system is further configured to selectively couple any of the plurality of I/O blocks to the microprocessor.

19. The programmable system of claim 15, wherein the global mapping system is further configured to selectively couple any of the plurality of I/O blocks with a different functional unit of the analog functional units and the digital functional units for each of a plurality of clock cycles.

20. The programmable system of claim 15, wherein the reconfigurable digital circuitry comprises a plurality of digital functional units each comprising a plurality of selectable logic circuits, wherein each of the plurality of digital functional units is reconfigurable to perform any of a plurality of predetermined digital functions, wherein the reconfigurable analog circuitry is reconfigurable to perform any of a plurality of analog functions, and wherein the reconfigurable analog circuitry comprises:

one or more continuous time blocks, wherein for each continuous time block of the one or more continuous time blocks, the continuous time block is configured to generate an output reflecting changes in an analog signal that varies continuously over time and that is supplied as an input to the continuous time block, and

one or more switched capacitor blocks.