Semiconductor device and method of manufacturing the same

• US 9,773,794 B2
• Filed: 05/24/2016
• Issued: 09/26/2017
• Est. Priority Date: 02/05/2014
• Status: Expired due to Fees

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Inventors: Sashida, Naoya
• Primary Examiner(s): Doan, Theresa T
• Application Number:
  US15/163,564
• Publication Number:
  US 20160268272A1
• Time in Patent Office: 490 Days
• Field of Search: 257296, 257532, 438238-239
• CPC Class Codes: G11C 11/221 using ferroelectric capacitors
• CPC Class Codes: H10B 53/30 characterised by the memory core region

Abstract

An embodiment of a semiconductor device includes a plate line that is connected to ferroelectric capacitors selected from a plurality of ferroelectric capacitors and covers the selected ferroelectric capacitors and regions between the selected ferroelectric capacitors from above top electrodes.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming a plurality of ferroelectric capacitors, each of the ferroelectric capacitors including a bottom electrode, a capacitor insulating film, and an top electrode;

forming a plurality of switching elements, each of the switching elements being connected to one of the ferroelectric capacitors, respectively;

forming a plurality of word lines, each of the word lines switching on and off two or more of the switching elements;

forming a plurality of bit lines, each of the bit lines being connected to two or more of the switching elements; and

forming a plate line that is connected to ferroelectric capacitors selected from the plurality of ferroelectric capacitors and covers the selected ferroelectric capacitors and regions between the selected ferroelectric capacitors from above the top electrodes, wherein

the plurality of ferroelectric capacitors is within an outline of the plate line in a plan view.

2. The method according to claim 1, wherein

ferroelectric capacitors connected to two or more of the switching elements that are switched on and off by the individual word lines are included in the selected ferroelectric capacitors, and

ferroelectric capacitors connected to two or more of the switching elements connected to the individual bit lines are included in the selected ferroelectric capacitors.

3. The method according to claim 1, wherein a catalytic activity, of a material of the plate line, that activates a substance that reduces the capacitor insulating film is lower than a catalytic activity, of a material of the top electrode, that activates a substance that reduces the capacitor insulating film.

4. The method according to claim 3, wherein the material of the plate line is aluminum, copper, tungsten, titanium, or titanium nitride, or any combination thereof.

5. The method according to claim 3, wherein the material of the top electrode is iridium, platinum, or strontium, or any combination thereof.

6. The method according to claim 1, further comprising forming a plurality of wiring layers above the top electrodes,

wherein the plate line is included in a wiring layer disposed at the lowermost position among the plurality of wiring layers.

7. The method according to claim 1, further comprising forming an interlayer insulating film between the top electrodes and the plate line,

wherein the top electrodes and the plate line are electrically connected via openings in the interlayer insulating film.

8. The method according to claim 1, wherein the bit lines are formed below the ferroelectric capacitors.

9. The method according to claim 1, further comprising forming a protective film that directly covers the ferroelectric capacitors.