Integrated circuit with heterogeneous CMOS integration of strained silicon germanium and group III-V semiconductor materials and method to fabricate same

• US 9,773,812 B2
• Filed: 01/10/2017
• Issued: 09/26/2017
• Est. Priority Date: 10/09/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Cheng-Wei, Hashemi, Pouya, Leobandung, Effendi, Reznicek, Alexander
• Primary Examiner(s): Luke, Daniel
• Assistant Examiner(s): RAHMAN, KHATIB A
• Application Number:
  US15/402,359
• Publication Number:
  US 20170125445A1
• Time in Patent Office: 259 Days
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds

Abstract

A structure includes an off-axis Si substrate with an overlying s-Si_1−xGe_x layer and a BOX between the off-axis Si substrate and the s-Si_1−xGe_x layer. The structure further includes pFET fins formed in the s-Si_1−xGe_x layer and a trench formed through the s-Si_1−xGe_x layer, the BOX and partially into the off-axis Si substrate. The trench contains a buffer layer in contact with the off-axis Si substrate, a first Group III-V layer disposed on the buffer layer, a semi-insulating Group III-V layer disposed on the first Group III-V layer and a second Group III-V layer disposed on the semi-insulating Group III-V layer, as well as nFET fins formed in the second Group III-V layer. The s-Si_1−xGe_x layer has a value of x that results from a condensation process that merges an initial s-Si_1−xGe_x layer with an initial underlying on-axis <100> Si layer. A method to fabricate the structure is also disclosed.

Claims

1. A structure comprising:

an off-axis Si substrate having an overlying s-Si<sub>1−

x</sub>Ge_x layer and a buried oxide layer disposed between the off-axis Si substrate and the s-Si<sub>1−

x</sub>Ge_x layer;

a first plurality of pFET fins formed in the s-Si<sub>1−

x</sub>Ge_x layer;

a trench formed through the s-Si<sub>1−

x</sub>Ge_x layer, the buried oxide layer and partially into the off-axis Si substrate, the trench containing a buffer layer in contact with the off-axis Si substrate, a first Group III-V layer disposed on the buffer layer, a semi-insulating Group III-V layer disposed on the first Group III-V layer and a second Group III-V layer disposed on the semi-insulating Group III-V layer; and

a first plurality of nFET fins formed in the second Group III-V layer.

2. The structure as in claim 1, further comprising a dielectric spacer disposed on vertical sidewalls of the trench.

3. The structure as in claim 1, where the s-Si₁₋

xGe_x layer has a value of x that results from a condensation process that merges an initial s-Si<sub>1−

x</sub>Ge_x layer having an initial value of x with an underlying initial on-axis <

100>

Si layer, where the initial value of x is less than the value of x in the s-Si<sub>1−

x</sub>Ge_x layer.

4. The structure as in claim 1, further comprising a second plurality of pFET fins formed in the s-Si₁₋

xGe_x layer, where the value of x in the first plurality of pFET fins is different than a value of x in the second plurality of pFET fins.

5. The structure as in claim 1, further comprising a second trench formed through the s-Si₁₋

xGe_x layer, the buried oxide layer and partially into the off-axis Si substrate, the second trench containing a buffer layer in contact with the off-axis Si substrate, a first Group III-V layer disposed on the buffer layer, a semi-insulating Group III-V layer disposed on the first Group III-V layer and a second Group III-V layer disposed on the semi-insulating Group III-V layer; and

a second plurality of nFET fins formed in the second Group III-V layer of the second trench.

6. The structure as in claim 5, where the second Group III-V layer disposed in the second trench is compositionally different than the second Group III-V layer disposed in the first trench.

7. The structure as in claim 1, where the semi-insulating Group III-V layer is comprised of Fe-doped InP.

8. The structure as in claim 1, where the off-axis Si substrate is a <

100>

Si substrate provided with about a 2°

to about a 6°

off cut obtained by rotation about a <

011>

axis.