Display panel and pixel array thereof
First Claim
1. A pixel array disposed on an array substrate, the pixel array comprising:
- a plurality of pixel rows, each of the pixel rows comprising;
a first gate line;
a second gate line, wherein the first gate line and the second gate line are arranged alternately along a first direction in sequence; and
a plurality of sub-pixels disposed between the first gate line and the second gate line along a second direction, wherein a portion of the sub-pixels are electrically connected with the first gate line, and the other portion of the sub-pixels are electrically connected with the second gate line; and
a plurality of data lines, each comprising;
a main portion, extending continuously to overlap at least two adjoining pixel rows between a first gate line of one of the plurality of pixel rows and a second gate line of another one of the plurality of pixel rows along the first direction;
at least one connecting portion, extending from the main portion without interrupting the main portion, disposed between the first gate line and the second gate line of the same pixel row, and electrically connected with the main portion; and
at least one branch portion, electrically connected with the at least one connecting portion, wherein;
main portions of the data lines are arranged along the second direction in sequence, and the main portions of the data lines intersect the first gate line and the second gate line;
branch portions and the main portions of the data lines are arranged alternately along the second direction, and each of the sub-pixels is disposed between any two of the main portion and the branch portion adjoining to each other; and
the at least one connecting portion penetrates through the sub-pixel disposed between the main portion and the branch portion along the second direction.
1 Assignment
0 Petitions
Accused Products
Abstract
A pixel array includes pixel rows. Each pixel row includes a first gate line, a second gate line, sub-pixels and data lines. Each data line includes a main portion, a branch portion and a connecting portion. The main portions of the data lines are arranged along a second direction in sequence. The branch portions and the main portions of the data lines are arranged alternately along the second direction in sequence, and each sub-pixel is disposed between any two of the adjoining main portion and branch portion. The connecting portion of each of the data lines is disposed between the first gate line and the second gate line, the connecting portion of each data line is electrically connected with the main portion and the branch portion of each data line, and the connecting portion of each data line penetrates through the corresponding sub-pixel along the second direction.
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Citations
16 Claims
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1. A pixel array disposed on an array substrate, the pixel array comprising:
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a plurality of pixel rows, each of the pixel rows comprising; a first gate line; a second gate line, wherein the first gate line and the second gate line are arranged alternately along a first direction in sequence; and a plurality of sub-pixels disposed between the first gate line and the second gate line along a second direction, wherein a portion of the sub-pixels are electrically connected with the first gate line, and the other portion of the sub-pixels are electrically connected with the second gate line; and a plurality of data lines, each comprising; a main portion, extending continuously to overlap at least two adjoining pixel rows between a first gate line of one of the plurality of pixel rows and a second gate line of another one of the plurality of pixel rows along the first direction; at least one connecting portion, extending from the main portion without interrupting the main portion, disposed between the first gate line and the second gate line of the same pixel row, and electrically connected with the main portion; and at least one branch portion, electrically connected with the at least one connecting portion, wherein; main portions of the data lines are arranged along the second direction in sequence, and the main portions of the data lines intersect the first gate line and the second gate line; branch portions and the main portions of the data lines are arranged alternately along the second direction, and each of the sub-pixels is disposed between any two of the main portion and the branch portion adjoining to each other; and the at least one connecting portion penetrates through the sub-pixel disposed between the main portion and the branch portion along the second direction. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A pixel array disposed on an array substrate, the pixel array comprising:
a plurality of pixel rows, each of the pixel rows comprising; a first gate line; a second gate line, wherein the first gate line and the second gate line are arranged alternately along a first direction in sequence; a plurality of sub-pixels disposed between the first gate line and the second gate line along a second direction, each comprising; an active switching device, comprising a gate electrode, a drain electrode and a source electrode; and a pixel electrode, electrically connected with the drain electrode of the active switching device, wherein a portion of the sub-pixels are electrically connected with the first gate line, and the other portion of the sub-pixels are electrically connected with the second gate line; and a plurality of data lines, each comprising a main portion, a branch portion and a connecting portion, wherein; main portions of the data lines are arranged along the second direction in sequence, and the main portions of the data lines intersect the first gate line and the second gate line; branch portions and the main portions of the data lines are arranged alternately along the second direction, and each of the sub-pixels is disposed between any two of the main portion and the branch portion adjoining to each other; and the connecting portion of each of the data lines is disposed between the first gate line and the second gate line, the connecting portion of each of the data lines is electrically connected with the main portion and the branch portion, and the connecting portion of each of the data lines penetrates through the sub-pixel disposed between the main portion and the branch portion along the second direction, wherein in each of the pixel rows, gate electrodes of active switching devices of (6n−
5)th numbered sub-pixels of the plurality of sub-pixels, gate electrodes of active switching devices of (6n−
2)th numbered sub-pixels of the plurality of sub-pixels, and gate electrodes of active switching devices of (6n)th numbered sub-pixels of the plurality of sub-pixels are electrically connected with the first gate line, gate electrodes of active switching devices of (6n−
4)th numbered sub-pixels of the plurality of sub-pixels, gate electrodes of active switching devices of (6n−
3)th numbered sub-pixels of the plurality of sub-pixels, and gate electrodes of active switching devices of (6n−
1)th numbered sub-pixels of the plurality of sub-pixels are electrically connected with the second gate line, and n is a set of integers greater than 0.
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16. A pixel array disposed on an array substrate, the pixel array comprising:
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a passivation layer; a common electrode disposed on the passivation layer; a plurality of pixel rows, each of the pixel rows comprising; a first gate line; a second gate line, wherein the first gate line and the second gate line are arranged alternately along a first direction in sequence; a plurality of sub-pixels disposed between the first gate line and the second gate line along a second direction, each comprising a pixel electrode disposed on the common electrode, wherein a portion of the sub-pixels are electrically connected with the first gate line, and the other portion of the sub-pixels are electrically connected with the second gate line; and a plurality of data lines, each comprising a main portion, a branch portion and a connecting portion; and an insulating layer disposed between the common electrode and pixel electrodes of the sub-pixels, wherein; main portions of the data lines are arranged along the second direction in sequence, and the main portions of the data lines intersect the first gate line and the second gate line; branch portions and the main portions of the data lines are arranged alternately along the second direction, and each of the sub-pixels is disposed between any two of the main portion and the branch portion adjoining to each other; and the connecting portion of each of the data lines is disposed between the first gate line and the second gate line, the connecting portion of each of the data lines is electrically connected with the main portion and the branch portion, and the connecting portion of each of the data lines penetrates through the sub-pixel disposed between the main portion and the branch portion along the second direction.
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Specification