Non-volatile static random access memory devices and methods of operations

• US 9,779,814 B2
• Filed: 08/09/2011
• Issued: 10/03/2017
• Est. Priority Date: 08/09/2011
• Status: Active Grant

• Current Assignee: Synerger Incorporated
• Original Assignee: Flashsilicon, Incorporation
• Inventors: Wang, Lee
• Primary Examiner(s): Graham, Kretelia
• Application Number:
  US13/206,270
• Publication Number:
  US 20130039127A1
• Time in Patent Office: 2,247 Days
• Field of Search: 36518508, 36518507, 365154, 36523005
• CPC Class Codes: G11C 14/0054 in which the volatile element is a SRAM cell
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor

Abstract

Non-Volatile Static Random Access Memory (NVSRAM) cell devices applying only one single non-volatile element embedded in a conventional Static Random Access Memory (SRAM) cell are disclosed. The NVSRAM cell devices can be integrated into a compact cell array. The NVSRAM devices of the invention have a read/write speed of a conventional SRAM and non-volatile property of a non-volatile memory cell. The methods of operations for the NVSRAM devices of the invention are also disclosed.

Claims

1. A non-volatile static random access memory (NVSRAM) device with a single semiconductor non-volatile memory element, comprising:

an SRAM element comprising;

a latch having a first output node and a second output node for retaining a data bit; and

two access transistors whose gates are connected together to form a word line, one of the two access transistors being connected between the first output node and one of a bit line pair, the other access transistor being connected between the second output node and the other of the bit line pair; and

the single semiconductor non-volatile memory element being a single-transistor type consisting of four terminals which are a first source/drain electrode, and a second source/drain electrode, a control gate electrode and a body electrode, wherein the first source/drain electrode is connected to a voltage line only and the second source/drain electrode is directly connected to both one of the two output nodes and one of the two access transistors without any switching transistor connected between the voltage line and the one of the two output nodes;

wherein a predetermined datum is written to the latch from the bit line pair to cause the one of the output nodes to have a default voltage by turning on the two access transistors, the latch and the single semiconductor non-volatile memory element are isolated from the bit line pair by turning off the two access transistors, one of a ground voltage and an operating voltage of the SRAM element is applied to the voltage line, and an intermediate voltage is applied to a control gate of the single semiconductor non-volatile memory element to enable the non-volatile data bit stored in the single semiconductor non-volatile memory element to be written to the SRAM element; and

wherein the intermediate voltage is between a first threshold voltage and a second threshold voltage of the single semiconductor non-volatile memory element.

2. The NVSRAM device according to claim 1, wherein the latch comprises two cross-coupled inverters.

3. The NVSRAM device according to claim 2, wherein the two cross-coupled inverters comprise a first inverter and a second inverter, wherein the first inverter comprises a first P-type MOSFET and a first N-type MOSFET and the second inverter comprises a second P-type MOSFET and a second N-type MOSFET, wherein gates of the first P-type MOSFET and the first N-type MOSFET and drains of the second P-type MOSFET and the second N-type MOSFET are connected together to form the second output node, and wherein gates of the second P-type MOSFET and the second N-type MOSFET and drains of the first P-type MOSFET and the first N-type MOSFET are connected together to form the first output node.

4. The NVSRAM device according to claim 1, wherein when the latch reads data from the bit line pair or writes data to the bit line pair, the single semiconductor non-volatile memory element is turned off so that the single semiconductor non-volatile memory element is isolated from the SRAM element.

5. The NVSRAM device according to claim 1, wherein the NVSRAM device operates as an individual SRAM element does when the single semiconductor non-volatile memory element is turned off.

6. A method of loading an non-volatile storing data bit from a single semiconductor non-volatile memory element into an SRAM element in a non-volatile static random access memory (NVSRAM) device with the single semiconductor non-volatile memory element, the SRAM element comprising a latch and two access transistors, the latch having a first output node and a second output node, gates of the two access transistors being connected together to form a word line, one of the two access transistors being connected between the first output node and one of a bit line pair, the other access transistor being connected between the second output node and the other of the bit line pair, the single semiconductor non-volatile memory element being a single-transistor type consisting of four terminals which are a first source/drain electrode, a second source/drain electrode, a control gate electrode and a body electrode, wherein the first source/drain electrode is connected to a voltage line only and the second source/drain electrode is directly connected to both a connecting node and one of the two access transistors without any switching transistor connected between the voltage line and the connecting node, the connecting node being one of the two output nodes, the method comprising:

writing a predetermined datum to the latch from the bit line pair to cause the connecting node to have a default voltage by turning on the two access transistors;

isolating the latch and the single semiconductor non-volatile memory element from the bit line pair by turning off the two access transistors;

applying one of a ground voltage and an operating voltage of the SRAM element to the voltage line; and

applying an intermediate voltage to a control gate of the single semiconductor non-volatile memory element to enable the non-volatile data bit stored in the single semiconductor non-volatile memory element to be written to the SRAM element;

wherein the intermediate voltage is between a first threshold voltage and a second threshold voltage of the single semiconductor non-volatile memory element.

7. The method according to claim 6, further comprising:

isolating the single semiconductor non-volatile memory element from the SRAM element by turning off the single semiconductor non-volatile memory element after the step of applying the intermediate voltage.

8. The method according to claim 6, further comprising:

selectively providing the predetermined datum on the bit line pair by means of an SRAM write circuit before the step of writing.

9. The method according to claim 6, wherein the step of applying one of the ground voltage and the operating voltage comprises:

applying the ground voltage to the voltage line if the single semiconductor non-volatile memory element is N-type, otherwise applying the operating voltage to the voltage line.

10. The method according to claim 6, wherein the default voltage is the operating voltage if the single semiconductor non-volatile memory element is N-type, otherwise the default voltage is the ground voltage.

11. The method according to claim 10, wherein the first threshold voltage is less than the second threshold voltage.

12. The method according to claim 11, further comprising:

causing the single semiconductor non-volatile memory element having the first threshold voltage to be turned on to set the connecting node to the ground voltage if the single semiconductor non-volatile memory element is N-type, otherwise causing the single semiconductor non-volatile memory element having the first threshold voltage to be turned on to set the connecting node to the operating voltage after the step of applying the intermediate voltage.

13. The method according to claim 11, further comprising:

causing the single semiconductor non-volatile memory element having the second threshold voltage to be turned off to maintain the default voltage at the connecting node after the step of applying the intermediate voltage.

14. The method according to claim 6, wherein the SRAM element is a six-transistor SRAM element or a two-resistor-four-transistor SRAM element.