Calibration methods and circuits to calibrate drive current and termination impedance

• US 9,780,784 B2
• Filed: 06/24/2016
• Issued: 10/03/2017
• Est. Priority Date: 09/08/2003
• Status: Active Grant

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Nguyen, Huy M., Gadde, Vijay, Lau, Benedict
• Primary Examiner(s): Owens, Douglas W
• Assistant Examiner(s): CHO, JAMES HYONCHOL
• Application Number:
  US15/191,840
• Publication Number:
  US 20170012623A1
• Time in Patent Office: 466 Days
• Field of Search: None
• CPC Class Codes: H03K 19/0005 Modifications of input or output impedance
• CPC Class Codes: H03K 19/01 Modifications for accelerating switching
• CPC Class Codes: H03K 21/08 Output circuits
• CPC Class Codes: H03K 5/24 the characteristic being amplitude
• CPC Class Codes: H04L 25/0278 Arrangements for impedance matching
• CPC Class Codes: H04L 25/0298 Arrangement for terminating transmission lines

Abstract

Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

Claims

1. An on-die termination (ODT) control circuit comprising:

at least one reference-voltage node;

a reference ODT resistor to exhibit a calibrated voltage responsive to an ODT count;

a comparator having a first comparator input, a second comparator input, and a comparator output;

a first pass gate selectively coupling the first comparator input to the at least one reference-voltage node;

a second pass gate selectively coupling the second comparator input to the reference ODT resistor to receive the calibrated voltage;

a third pass gate selectively coupling the second comparator input to the at least one reference-voltage node; and

a counter coupled between the comparator output and the reference ODT resistor, the counter to issue the ODT count responsive to an output of the comparator.

2. The ODT control circuit of claim 1, further comprising a voltage source between the at least one reference-voltage node and the second comparator input.

3. The ODT control circuit of claim 2, the at least one reference-voltage node comprising a reference-voltage node coupled to the first comparator input and selectively coupled to the second comparator input via the voltage source.

4. The ODT control circuit of claim 1, further comprising a latch coupled between the comparator output and the counter.

5. The ODT control circuit of claim 1, further comprising a filter coupled between the comparator output and the counter.

6. The ODT control circuit of claim 1, further comprising a current source coupled to the reference ODT resistor, the current source to draw a current through the reference ODT resistor to develop the calibrated voltage, wherein the calibrated voltage is a function of the ODT count and the current.

7. The ODT control circuit of claim 6, further comprising a second counter coupled to the comparator output and the current source, the second counter to issue a current-control count responsive to the output of the comparator.

8. The ODT control circuit of claim 6, further comprising a transistor selectively coupling the current source to the reference ODT resistor.

9. A method for calibrating a resistance of an on-die termination (ODT) resistor using a single comparator, the method comprising:

pulling a current from a reference-voltage node through a reference resistor to produce a reference-resistor voltage;

applying the reference-resistor voltage to a first input of the comparator;

adjusting a second voltage on a second input of the comparator, responsive to an output of the comparator, to set the second voltage equal to the reference-resistor voltage;

coupling the ODT resistor to the first input of the comparator; and

adjusting the resistance of the ODT resistor, responsive to an output of the comparator, to set a voltage from the ODT resistor equal to the second voltage.

10. The method of claim 9, further comprising calibrating a current through the ODT resistor using the comparator.

11. The method of claim 10, wherein calibrating the current comprises drawing the current through the reference resistor to adjust the second voltage on a second input of the comparator, responsive to an output of the comparator, to set the second voltage equal to the reference-resistor voltage.

12. The method of claim 10, wherein calibrating the current comprises adjusting a current source responsive to the output from the comparator.

13. The method of claim 9, further comprising accumulating the output of the comparator in a counter, wherein the adjusting the resistance of the ODT resistor is responsive to the accumulated output.

14. The method of claim 13, further comprising distributing the accumulated output to termination elements.

15. An on-die termination (ODT) control circuit comprising:

a first reference-voltage node to provide a first reference voltage;

a reference ODT resistor to exhibit a calibrated resistance that provides a calibrated voltage responsive to an ODT count;

a comparator having a first comparator input coupled to the first reference-voltage node to receive the first reference voltage, a second comparator input, and a comparator output;

a multiplexer having a first multiplexer input coupled the reference ODT resistor to receive the calibrated voltage, a second multiplexer input to receive a second reference voltage, and a multiplexer output coupled to the second comparator input; and

a counter coupled between the comparator output and the reference ODT resistor, the counter to issue the ODT count responsive to an output of the comparator.

16. The ODT control circuit of claim 15, wherein the second multiplexer input is coupled to a second reference-voltage node.

17. The ODT control circuit of claim 16, wherein the second reference-voltage node applies a second reference voltage offset from a voltage source between the first reference-voltage node and the second reference-voltage node.

18. The ODT control circuit of claim 15, further comprising a latch coupled between the comparator output and the counter.

19. The ODT control circuit of claim 15, further comprising a filter coupled between the comparator output and the counter.