Display substrate and manufacturing method thereof

• US 9,791,758 B2
• Filed: 07/20/2015
• Issued: 10/17/2017
• Est. Priority Date: 03/13/2015
• Status: Active Grant

• Current Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Original Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Inventors: Li, Tiansheng
• Primary Examiner(s): Lee, Kyoung
• Assistant Examiner(s): SYLVIA, CHRISTINA A
• Application Number:
  US14/908,673
• Publication Number:
  US 20170038622A1
• Time in Patent Office: 820 Days
• CPC Class Codes: G02F 1/1368 in which the switching element is a three-electrode device G02F1/136277 takes precedence
• CPC Class Codes: G02F 2201/123 pixel
• CPC Class Codes: H01L 21/77 Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate electrically programmable read-only memories or multistep manufacturing processes therefor H10B69/00
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1244 for preventing breakage, peeling or short circuiting
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

The present invention provides a display substrate and a manufacturing method thereof. The display substrate of the present invention comprises a first structure and a second structure; wherein, the second structure is provided with a lap portion disposed on the first structure and a main body portion connected with the lap portion and outside the first structure; the first structure has a thinned region connected to an edge thereof, and a thickness of the first structure in the thinned region is smaller than that outside the thinned region; and at least part of the lap portion is located on the thinned region, and at least part of the main body portion outside the thinned region is in direct connection with the part of the lap portion on the thinned region.

Claims

1. A display substrate, comprising a first structure and a second structure;

wherein, the second structure is provided with a lap portion disposed on the first structure, and a main body portion disposed outside the first structure and connected with the lap portion;

the first structure has a thinned region connected to an edge thereof, and a thickness of the first structure in the thinned region is smaller than that of the first structure outside the thinned region; and

at least part of the lap portion is located on the thinned region, and at least part of the main body portion outside the thinned region is in direct connection with the part of the lap portion on the thinned region,

wherein, a part, which is covered by the lap portion, of the thinned region comprises a plurality of sub-thinned regions, and the first structure in a sub-thinned region closer to the edge thereof has a smaller thickness.

2. The display substrate according to claim 1, wherein,

the display substrate is an array substrate, the first structure is a drain of a thin film transistor, and the second structure is a pixel electrode.

3. The display substrate according to claim 2, wherein,

the drain is entirely disposed on an active region.

4. The display substrate according to claim 3, wherein,

the lap portion covers the entire thinned region.

5. The display substrate according to claim 3, wherein,

the thickness of the first structure in the thinned region is a half to two thirds of that of the first structure outside the thinned region.

6. The display substrate according to claim 2, wherein,

the lap portion covers the entire thinned region.

7. The display substrate according to claim 2, wherein,

the thickness of the first structure in the thinned region is a half to two thirds of that of the first structure outside the thinned region.

8. The display substrate according to claim 1, wherein,

the display substrate further comprises a base, and a distance between the first structure and the base is larger than or equal to that between the main body portion of the second structure and the base.

9. The display substrate according to claim 1, wherein,

the lap portion covers the entire thinned region.

10. The display substrate according to claim 1, wherein,

the thickness of the first structure in the thinned region is a half to two thirds of that of the first structure outside the thinned region.

11. A manufacturing method of a display substrate, comprising:

step 1;

forming a first structure such that the first structure has a thinned region adjacent to an edge thereof, and

step 2;

forming a second structure such that the second structure has a lap portion disposed on the first structure and a main body portion disposed outside the first structure and connected with the lap portion, wherein at least part of the lap portion is located on the thinned region; and

at least part of the main body portion outside the thinned region is in direct connection with the part of the lap portion on the thinned region,

wherein, the thinned region formed in step 1 comprises a plurality of sub-thinned regions which are thinned to different degrees in different regions, so that a sub-thinned region closer to the edge of the first structure is thinned to a larger degree; and

the lap portion formed in the step 2 covers the plurality of sub-thinned regions.

12. The manufacturing method according to claim 11, wherein, forming the first structure in the step 1 comprises:

covering with a photoresist and performing dry etching so that the first structure is provided with the thinned region adjacent to the edge thereof.

13. The manufacturing method according to claim 11, wherein,

in the step 1, the first structure is formed by stepwise exposure in one patterning process so that the first structure is provided with the thinned region adjacent to the edge thereof.

14. The manufacturing method according to claim 11, wherein,

the display substrate is an array substrate, the first structure is a drain of a thin film transistor, and the second structure is a pixel electrode.

15. The manufacturing method according to claim 14, wherein,

in the step 1, an active region of the thin film transistor is also formed at the same time and the drain is entirely disposed on the active region.

16. A manufacturing method of a display substrate, comprising:

step 1;

forming a first structure such that the first structure has a thinned region adjacent to an edge thereof; and

step 2;

forming a second structure such that the second structure has a lap portion disposed on the first structure and a main body portion disposed outside the first structure and connected with the lap portion, wherein at least part of the lap portion is located on the thinned region; and

at least part of the main body portion outside the thinned region is in direct connection with the part of the lap portion on the thinned region,

wherein, the display substrate is an array substrate, the first structure is a drain of a thin film transistor, and the second structure is a pixel electrode,

wherein, in the step 1, an active region of the thin film transistor is also formed at the same time and the drain is entirely disposed on the active region,

wherein, the step 1 comprises;

sequentially forming a semiconductor layer, a source-drain metal layer and a photoresist layer on a base;

performing stepwise exposure and development on the photoresist layer so that the photoresist layer has a first thickness in a first region, has a second thickness in a second region, has a third thickness in a third region, and does not remain in the remaining region;

wherein, the first region corresponds to an area of the active region which is conductive when the thin film transistor is turned on, the second region corresponds at least to the thinned region of the drain, and the third region corresponds at least to an area of the active region other than the first region and the second region, the first thickness is smaller than the second thickness, and the second thickness is smaller than the third thickness;

removing parts of the source-drain metal layer and the semiconductor layer which are not covered by the photoresist, so as to form the active region;

performing ashing on the photoresist layer, so as to remove the photoresist layer in the first region, and preserve parts of the photoresist layer in the second region and the third region;

removing the source-drain metal layer in the first region, so as to form a source and the drain;

performing ashing on the photoresist layer to remove the photoresist layer in the second region and preserve a part of the photoresist layer in the third region;

thinning the source-drain metal layer in the second region to form the thinned region; and

removing the photoresist layer in the third region.