Method, apparatus, and system for energy efficiency and energy conservation including autonomous hardware-based deep power down in devices

• US 9,792,064 B2
• Filed: 07/25/2016
• Issued: 10/17/2017
• Est. Priority Date: 12/22/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Sodhi, Inder M., Naveh, Alon, Rajwan, Doron, Wells, Ryan D., Samson, Eric C.
• Primary Examiner(s): TRAN, VINCENT HUY
• Application Number:
  US15/219,183
• Publication Number:
  US 20160335020A1
• Time in Patent Office: 449 Days
• Field of Search: 713323
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/3278 Power saving in modem or I/O interface
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Embodiments of systems, apparatuses, and methods for energy efficiency and energy conservation including enabling autonomous hardware-based deep power down of devices are described. In one embodiment, a system includes a device, a static memory, and a power control unit coupled with the device and the static memory. The system further includes a deep power down logic of the power control unit to monitor a status of the device, and to transfer the device to a deep power down state when the device is idle. In the system, the device consumes less power when in the deep power down state than in the idle state.

Claims

1. A system for efficient energy consumption, comprising:

a device external to a central processing unit (CPU);

a static memory dedicated to the device;

a sustain power rail to provide power to the static memory to enable the static memory to maintain its storage during a deep power down state; and

a power control unit coupled with the device and the static memory, the power control unit to monitor a plurality of metrics and to select a heuristic to employ to control power transfers, and to transfer the device to a deep power down state when the device is idle, wherein the device consumes less power in the deep power down state than in the idle state.

2. The system of claim 1, wherein the power control unit is further to store context data obtained from the device in the static memory when the device is transferred to the deep power down state.

3. The system of claim 2, further comprising:

in response to the power control unit monitoring an event, the power control unit to wake the device, wherein the power control unit transfers the device to an active state and loads the context data from the static memory into the device.

4. The system of claim 3, wherein the event is a processor of the system waking from an idle state.

5. The system of claim 3, wherein the event is an event to be processed by the device, and where a processor of the system remains in an idle state.

6. The system of claim 1, wherein the power control unit initiates the transfer of the device to the deep power down state when a processor of the system enters into an idle state.

7. The system of claim 1, wherein the power control unit initiates the transfer of the device to the deep power down state when a processor of the system is in an active state.

8. The system of claim 1, wherein the power control unit is to employ a first heuristic during a first time interval, and employ a second, different heuristic during a second time interval.

9. A method for efficient energy consumption in a system, comprising:

monitoring a status of a device external to a central processing unit (CPU);

providing power to a static memory dedicated to the device using a sustain power rail to enable the static memory to maintain its storage during a deep power down state; and

monitoring, by a power control unit coupled with the device and the static memory, a plurality of metrics;

the power control unit further to;

periodically select a heuristic to employ to control power transfers; and

transfer the device to a deep power down state when the device is idle, wherein the device consumes less power in the deep power down state than in the idle state.

10. The method of claim 9, further comprising:

storing context data obtained from the device in the static memory when the device is transferred to the deep power down state.

11. The method of claim 10, further comprising:

waking the device in response to monitoring an event;

transferring the device to an active state; and

loading the context data from the static memory into the device.

12. The method of claim 11, wherein the event is a processor of the system waking from an idle state.

13. The method of claim 11, wherein the event is an event to be processed by the device, and where a processor of the system remains in an idle state.

14. The method of claim 9, wherein the transfer of the device to the deep power down state is initiated when a processor of the system enters into an idle state.

15. A system for efficient energy consumption comprising:

a plurality of devices external to a central processing unit (CPU), including at least a graphics processing unit;

a static memory dedicated to the plurality of devices;

a power control unit coupled with the plurality of devices and the static memory, the power control unit to monitor a plurality of metrics including a status of at least one of the plurality of devices, transactions between at least one of the plurality of devices and the CPU, and accesses to registers included in at least one of the plurality of devices, wherein the power control unit is to select a heuristic, and, based on the selected heuristic, to transfer at least one of the plurality of devices from an idle state to a deep power down state.

16. The system of claim 15, wherein the transfer is transparent to an operating system of the CPU.

17. The system of claim 16, wherein the power control unit is further to periodically update the heuristic to employ to control power transfers.

18. The system of claim 15, wherein the at least one of the plurality of devices further comprises registers to store context data, and wherein the power control unit is further to cause the context data to be stored in the static memory when the device is transferred to the deep power down state.

19. The system of claim 18, wherein the power control unit is further to:

wake the device in response to monitoring an event, transfer the device to an active state, and load the context data from the static memory into the device, wherein the event is a processor of the system waking from an idle state.