Computer architecture to provide flexibility and/or scalability

• US 9,792,243 B2
• Filed: 12/26/2013
• Issued: 10/17/2017
• Est. Priority Date: 12/26/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Blevins, Dirk F., Morgan, John M., Goldschmidt, Marc A., Pullin, Edward J.
• Primary Examiner(s): Nam, Hyun
• Application Number:
  US14/140,718
• Publication Number:
  US 20150186319A1
• Time in Patent Office: 1,391 Days
• CPC Class Codes: G06F 13/20 for access to input/output bus
• CPC Class Codes: G06F 13/4068 Electrical coupling

Abstract

Apparatus, systems, and/or methods may include a peripheral component interconnect express (PCIe) link to directly couple a slot with a network fabric. The slot may be defined by a surface and/or may accommodate a hardware module. A rack unit implementation may be utilized, such as a one rack unit (1 U) implementation, a four rack unit (4 U) implementation, and so on. The network fabric may be utilized when hardware modules communicate across the PCIe link, may be bypassed when hardware modules communicate across an additional PCIe link, and so on. The PCIe link may include a direct connect point-to-point PCIe link, a dual star PCIe link, and so on. In addition, the PCIe link may be utilized in a rack-scale architecture.

Claims

1. A rack-scale architecture comprising:

a surface defining a slot to accommodate a hardware module; and

a peripheral component interconnect express (PCIe) fabric between the slot and

a network fabric, wherein the PCIe fabric is to include;

a PCIe link to directly couple the slot with the network fabric to provide a communication path including the network fabric; and

a further PCIe link to couple the slot with a further slot to provide a communication path excluding the network fabric, wherein the further slot is to accommodate a further hardware module,

wherein the rack-scale architecture is to include one or more of;

a one rack unit implementation, wherein at least one slot accommodates a respective processor module, and wherein an additional PCIe link is to directly couple the at least one slot with a back panel input/output (I/O);

a two rack unit implementation, wherein at least one slot accommodates a respective processor module, and wherein an additional PCIe link is to directly couple the at least one slot with a back panel I/O;

or

a four rack unit implementation, wherein at least one slot accommodates a respective processor module, and wherein an additional PCIe link is to directly couple the at least one slot with a back panel I/O.

2. The architecture of claim 1, further including an additional PCIe link to directly couple the further slot with the network fabric to provide an additional communication path.

3. The architecture of claim 1, further including:

at least two slots that accommodate a respective processor module, wherein the network fabric is to be utilized when the respective processor modules communicate across respective PCIe links directly coupling each of the at least two slots with the network fabric; and

at least two slots that accommodate a respective processor module, wherein the network fabric is to be bypassed when the respective processor modules communicate across respective further PCIe links directly coupling each of the at least two slots with a bridge external to the network fabric.

4. The architecture of claim 1, further including one or more of:

the further PCIe link is to directly couple a slot that accommodates a processor module with a slot that accommodates an I/O module, wherein the network fabric is to be bypassed when the processor module and the I/O module communicate across the further PCIe link;

or

the further PCIe link includes a dual star PCIe link to directly couple four slots with each other, wherein the network fabric is to be bypassed when at least two hardware modules communicate across the dual star PCIe link.

5. The architecture of claim 1, further including one or more of:

a user specific I/O to provide user defined functionality;

or

a management element to provide management functionality.

6. The architecture of claim 1, wherein the hardware module includes one or more of:

a processor module;

a storage module;

a networking module;

a security module;

a switch module;

a micro-server module;

a PCIe module;

a graphics module;

or

a general purpose I/O card.

7. The architecture of claim 1, further including one or more of:

a chassis including the surface defining the slot, wherein the chassis includes a standard size corresponding to a rack specification;

a form factor specific off the shelf module;

or

a form factor specific user defined module.

8. The architecture of claim 1, further including a backboard including one or more of:

a dynamic function backboard;

or

a fixed function backboard.

9. A method comprising:

providing a surface defining a slot to accommodate a hardware module, and

providing a peripheral component interconnect express (PCIe) fabric between the slot and a network fabric, wherein the PCIe fabric includes;

a peripheral component interconnect express (PCIe) link directly coupling the slot with the network fabric to provide a communication path including the network fabric, wherein the slot accommodates a hardware module; and

a further PCIe link to couple the slot with a further slot to provide a communication path excluding the network fabric, wherein the further slot accommodates a further hardware module; and

providing one or more of;

a one rack unit implementation, wherein at least one slot accommodates a respective processor module, and wherein an additional PCIe link directly couples the at least one slot with a back panel input/output (I/O);

a two rack unit implementation, wherein at least one slot accommodates a respective processor module, and wherein an additional PCIe link directly couples the at least one slot with a back panel I/O;

or

a four rack unit implementation, wherein at least one slot accommodates a respective processor module, and wherein an additional PCIe link directly couples the at least one slot with a back panel I/O.

10. The method of claim 9, further including:

providing at least two slots that accommodate a respective processor module, wherein the network fabric is utilized when the respective processor modules communicate across respective PCIe links directly coupling each of the at least two slots with the network fabric; and

providing at least two slots that accommodate a respective processor module, wherein the network fabric is bypassed when the respective processor modules communicate across respective further PCIe links directly coupling each of the at least two slots with a bridge external to the network fabric.

11. The method of claim 9, further including one or more of:

providing the further PCIe link directly coupling a slot that accommodates a processor module with a slot that accommodates an I/O module, wherein the network fabric is bypassed when the processor module and the I/O module communicate across the further PCIe link;

or

providing the further PCIe link including a dual star PCIe link directly coupling four slots with each other, wherein the network fabric is bypassed when at least two hardware modules communicate across the dual star PCIe link.

12. The method of claim 9, further including one or more of:

providing a user specific I/O to provide user defined functionality;

or

providing a management element to provide management functionality.

13. The method of claim 9, further including one or more of:

providing a chassis including the surfaces defining the slot, wherein the chassis includes a standard size corresponding to a rack implementation;

providing a form factor specific off the shelf module;

providing a form factor specific user defined module;

or

providing a backboard including one or more of a dynamic function backboard or a fixed function backboard.

14. At least one non-transitory computer-readable medium comprising one or more instructions that when executed on a computing device cause the computing device to:

provide a peripheral component interconnect express (PCIe) fabric between a slot and a network fabric, wherein the PCIe fabric is to include;

a PCIe link to directly couple the slot defined by a surface with the network fabric to provide a communication path including the network fabric, wherein the slot is to accommodate a hardware module; and

a further PCIe link to couple the slot with a further slot to provide a communication path excluding the network fabric, wherein the further slot is to accommodate a further hardware module; and

provide one or more of;

a one rack unit implementation, wherein at least one slot accommodates a respective processor module, and wherein an additional PCIe link directly couples the at least one slot with a back panel input/output (I/O);

a two rack unit implementation, wherein at least one slot accommodates a respective processor module, and wherein an additional PCIe link directly couples the at least one slot with a back panel I/O;

or

a four rack unit implementation, wherein at least one slot accommodates a respective processor module, and wherein an additional PCIe link directly couples the at least one slot with a back panel I/O.

15. The at least one medium of claim 14, wherein when executed the one or more instructions cause the computing device to:

provide at least two slots that accommodate a respective processor module, wherein the network fabric is to be utilized when the respective processor modules communicate across respective PCIe links directly coupling each of the at least two slots with the network fabric; and

provide at least two slots that accommodate a respective processor module, wherein the network fabric is to be bypassed when the respective processor modules communicate across respective further PCIe links directly coupling each of the at least two slots with a bridge external to the network fabric.

16. The at least one medium of claim 14, wherein when executed the one or more instructions cause the computing device to:

provide the further PCIe link to directly couple a slot that accommodates a processor module with a slot that accommodates an I/O module, wherein the network fabric is to be bypassed when the processor module and the I/O module communicate across the further PCIe link;

or

provide the further PCIe link including a dual star PCIe link to directly couple four slots with each other, wherein the network fabric is to be bypassed when at least two hardware modules communicate across the dual star PCIe link.

17. The at least one medium of claim 14, wherein when executed the one or more instructions cause the computing device to:

provide a user specific I/O to provide user defined functionality;

or

provide a management element to provide management functionality.

18. The at least one medium of claim 14, wherein when executed the one or more instructions cause the computing device to:

provide a chassis including the surfaces defining the slot, wherein the chassis includes a standard size corresponding to a rack specification;

provide a form factor specific off the shelf module;

provide a form factor specific user defined module;

or

provide a backboard including one or more of a dynamic function backboard or a fixed function backboard.

19. An apparatus comprising:

a surface defining a slot to accommodate a hardware module, and

logic to,

provide a peripheral component interconnect express (PCIe) fabric between the slot and a network fabric, wherein the PCIe fabric is to include,

a PCIe link to directly couple the slot with the network fabric to provide a communication path including the network fabric, and

a further PCIe link to couple the slot with a further slot to provide a communication path excluding the network fabric, wherein the further slot is to accommodate a further hardware module and

provide one or more of,

a one rack unit implementation, wherein at least one slot accommodates a respective processor module, and wherein an additional PCIe link directly couples the at least one slot with a back panel input/output (I/O);

a two rack unit implementation, wherein at least one slot accommodates a respective processor module, and wherein an additional PCIe link directly couples the at least one slot with a back panel I/O;

or

a four rack unit implementation, wherein at least one slot accommodates a respective processor module, and wherein an additional PCIe link directly couples the at least one slot with a back panel I/O.

20. The apparatus of claim 19, wherein the logic is to,

provide at least two slots that accommodate a respective processor module, wherein the network fabric is to be utilized when the respective processor modules communicate across respective PCIe links directly coupling each of the at least two slots with the network fabric, and

provide at least two slots that accommodate a respective processor module, wherein the network fabric is to be bypassed when the respective processor modules communicate across respective further PCIe links directly coupling each of the at least two slots with a bridge external to the network fabric.

21. The apparatus of claim 19, wherein the logic is to,

provide the further PCIe link to directly couple a slot that accommodates a processor module with a slot that accommodates an I/O module, wherein the network fabric is to be bypassed when the processor module and the I/O module communicate across the further PCIe link, or

provide the further PCIe link including a dual star PCIe link to directly couple four slots with each other, wherein the network fabric is to be bypassed when at least two hardware modules communicate across the dual star PCIe link.

22. The apparatus of claim 19, wherein the logic is to,

provide a chassis including the surfaces defining the slot, wherein the chassis includes a standard size corresponding to a rack specification,

provide a form factor specific off the shelf module,

provide a form factor specific user defined module, or

provide a backboard including one or more of a dynamic function backboard or a fixed function backboard.