Reducing latency in an expanded memory system

• US 9,812,186 B2
• Filed: 10/26/2015
• Issued: 11/07/2017
• Est. Priority Date: 04/27/2013
• Status: Active Grant

• Current Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Original Assignee: Huawei Technologies Co., Ltd. (Huawei Investment & Holding Co., Ltd.)
• Inventors: Ruan, Yuan, Chen, Mingyu
• Primary Examiner(s): BRAGDON, REGINALD GLENWOOD
• Assistant Examiner(s): Thomas, James J
• Application Number:
  US14/922,973
• Publication Number:
  US 20160055898A1
• Time in Patent Office: 743 Days
• Field of Search: None
• CPC Class Codes: G06F 12/02 Addressing or allocation; Relocation program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G11C 11/40607 Refresh operations in memory devices with an internal cache or data buffer
• CPC Class Codes: G11C 7/1063 Control signal output circuits, e.g. status or busy flags, feedback command signals
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

A first level buffer chip gates a target second level buffer chip according to a preset mapping relationship, a first chip select signal, and a first higher-order address signal, and forwards a memory access instruction and a lower-order address signal received from a memory controller to the target second level buffer chip. The target second level buffer chip determines a target memory module according to a second chip select signal and a delayed address signal obtained by delay processing on a second higher-order address signal, determines a target memory chip according to the lower-order address signal, acquires target data from the target memory chip according to the memory access instruction, and returns the target data to the memory controller. A cascading manner of a system memory is changed to a tree-like topological form, which avoids a protocol conversion problem and reduces the memory access time.

Claims

1. A memory access method, comprising:

sending, by a memory controller, a memory access instruction, a lower-order address signal, a first chip select signal, and a first higher-order address signal to a first level buffer chip, performing delay processing on a second higher-order address signal to obtain a delayed address signal, and sending the delayed address signal to a second level buffer chip, wherein;

the first level buffer chip is cascaded with the second level buffer chip,

the second level buffer chip is connected to at least one memory module, wherein the at least one memory module comprises at least one memory chip,

the first chip select signal and the first higher-order address signal are used to identify a target second level buffer chip in the second level buffer chip, and

the lower-order address signal is used to identify a target memory chip in a target memory module;

outputting, by the first level buffer chip, a second chip select signal to the second level buffer chip according to a preset mapping relationship, the first chip select signal, and the first higher-order address signal to gate the target second level buffer chip, and sending the memory access instruction and the lower-order address signal to the target second level buffer chip, wherein;

the second level buffer chip comprises at least one buffer chip, and

the target second level buffer chip is a buffer chip that is gated by using the second chip select signal and is in the second level buffer chip;

determining, by the target second level buffer chip, the target memory module from the at least one memory module according to the delayed address signal and the second chip select signal, and determining the target memory chip from the target memory module according to the lower-order address signal, wherein the delayed address signal and the second chip select signal are used to identify the target memory module in the at least one memory module; and

acquiring, by the target second level buffer chip, target data from the target memory chip according to the memory access instruction, and sending the target data to the memory controller by using the first level buffer chip.

2. The memory access method according to claim 1, wherein performing, by the memory controller, delay processing on a second higher-order address signal to obtain a delayed address signal comprises:

performing, by the memory controller, delay processing on the second higher-order address signal according to a delay parameter of the first level buffer chip to obtain the delayed address signal.

3. The memory access method according to claim 1, wherein outputting, by the first level buffer chip, a second chip select signal to the second level buffer chip according to a preset mapping relationship, the first chip select signal, and the first higher-order address signal to gate the target second level buffer chip comprises:

generating, by the first level buffer chip, code according to the mapping relationship;

coding, by the first level buffer chip, the first chip select signal and the first higher-order address signal by using the code, so as to obtain the second chip select signal; and

outputting, by the first level buffer chip, the second chip select signal to the second level buffer chip to gate the target second level buffer chip.

4. A memory system, comprising:

a memory controller, a first level buffer chip, and at least one second level buffer chip, wherein the memory controller is connected to the first level buffer chip and the at least one second level buffer chip, the first level buffer chip is cascaded with the at least one second level buffer chip, the at least one second level buffer chip is connected to at least one memory module, and the at least one memory module comprises at least one memory chip;

wherein the memory controller is configured to;

send a memory access instruction, a lower-order address signal, a first chip select signal, and a first higher-order address signal to the first level buffer chip,

perform delay processing on a second higher-order address signal to obtain a delayed address signal,

send the delayed address signal to the at least one second level buffer chip, and

receive target data returned by the first level buffer chip, wherein the first chip select signal and the first higher-order address signal are used to identify a target second level buffer chip in the at least one second level buffer chip, and the lower-order address signal is used to identify a target memory chip in a target memory module;

wherein the first level buffer chip is configured to;

receive the memory access instruction, the lower-order address signal, the first chip select signal, and the first higher-order address signal,

output a second chip select signal to the at least one second level buffer chip according to a preset mapping relationship, the first chip select signal, and the first higher-order address signal to gate the target second level buffer chip,

send the memory access instruction and the lower-order address signal to the target second level buffer chip,

receive the target data returned by the target second level buffer chip, and

send the target data to the memory controller, wherein the at least one second level buffer chip comprises at least one buffer chip, and the target second level buffer chip is a buffer chip that is gated by using the second chip select signal and is in the at least one second level buffer chip; and

wherein the target second level buffer chip is configured to;

receive the memory access instruction, the lower-order address signal, the delayed address signal, and the second chip select signal,

determine the target memory module from the at least one memory module according to the delayed address signal and the second chip select signal,

determine the target memory chip from the target memory module according to the lower-order address signal,

acquire the target data from the target memory chip according to the memory access instruction, and

send the target data to the first level buffer chip, wherein the delayed address signal and the second chip select signal are used to identify the target memory module in the at least one memory module.

5. The memory system according to claim 4, wherein the memory controller is configured to:

perform delay processing on the second higher-order address signal according to a delay parameter of the first level buffer chip to obtain the delayed address signal.

6. The memory system according to claim 4, wherein the first level buffer chip is configured to:

generate code according to the mapping relationship;

code the first chip select signal and the first higher-order address signal by using the code, so as to obtain the second chip select signal; and

output the second chip select signal to the at least one second level buffer chip to gate the target second level buffer chip.

7. The memory system according to claim 4, wherein the first level buffer chip is an isolation memory buffer (iMB) chip.

8. The memory system according to claim 4, wherein a load-reduced dual in-line (LRDIMM) comprises an isolation memory buffer (iMB) chip and the at least one memory module, the iMB chip in the LRDIMM is the at least one second level buffer chip.