Interconnect structure and manufacturing method thereof

• US 9,818,644 B2
• Filed: 04/01/2016
• Issued: 11/14/2017
• Est. Priority Date: 03/21/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yang, Shin-Yi, Tien, Hsi-Wen, Lee, Ming-Han, Lee, Hsiang-Huan, Shue, Shau-Lin
• Primary Examiner(s): Page, Dale E
• Assistant Examiner(s): Haider, Wasiul
• Application Number:
  US15/088,134
• Publication Number:
  US 20160218035A1
• Time in Patent Office: 592 Days
• CPC Class Codes: H01L 21/28556 by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/28562 Selective deposition
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76844 Bottomless liners
• CPC Class Codes: H01L 21/76876 for deposition from the gas phase, e.g. CVD
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 2221/1094 Conducting structures comprising nanotubes or nanowires
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53276 containing carbon, e.g. fullerenes superconducting fullerenes H10N60/853
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present disclosure provides an interconnect structure, including a substrate, a first conductive feature over the substrate, a second conductive feature over the first conductive feature, and a dielectric layer surrounding the first conductive feature and the second conductive feature. A width of the first conductive feature and a width of the second conductive feature are between 10 nm and 50 nm. The present disclosure also provides a method for manufacturing an interconnect structure, including (1) forming a via opening and a line trench in a dielectric layer, (2) forming a 1-dimensional conductive feature in the via opening, (3) forming a conformal catalyst layer over a sidewall of the line trench, a bottom of the line trench, and a top of the 1-dimensional conductive feature, and (4) removing the conformal catalyst layer from the bottom of the line trench and the top of the 1-dimensional conductive feature.

Claims

1. A method for manufacturing an interconnect structure, comprising:

forming a via opening and a line trench in a dielectric layer, wherein a width of the via opening and a width of the line trench are in a range of from about 10 nm to about 50 nm;

forming carbon nanotubes (CNTs) in the via opening;

forming a conformal catalyst layer over a sidewall of the line trench, a bottom of the line trench, and a top of the CNTs;

removing the conformal catalyst layer from the bottom of the line trench and the top of the CNTs; and

forming a 2-dimensional conductive feature in the line trench.

2. The method of claim 1, wherein the forming the CNTs in the via opening comprises performing a chemical vapor deposition (CVD), and the forming the 2-dimensional conductive feature in the line trench comprises performing a CVD.

3. The method of claim 1, wherein the forming the conformal catalyst layer comprises forming a metal layer with a thickness ranging from about 0.5 nm to about 2 nm by performing a physical vapor deposition, a chemical vapor deposition, or a combination thereof.

4. The method of claim 1, further comprising performing a chemical mechanical polishing to remove a portion of the 2-dimensional conductive feature and a portion of the conformal catalyst layer.

5. The method of claim 1, further comprising forming a catalyst layer at a bottom of the via opening prior to the forming of the CNTs.

6. The method of claim 5, wherein the catalyst layer comprises transition metal silicide or metal.

7. The method of claim 1, wherein the removing the conformal catalyst layer from the bottom of the line trench and the top of the CNTs comprises performing a dry etch.

8. A method for manufacturing a semiconductor structure, comprising:

forming a via opening and a line trench in a dielectric layer, the line trench being wider than the via opening;

forming a first conductive feature in the via opening;

forming a conformal catalyst layer over a sidewall of the line trench, a bottom of the line trench, and a top of the first conductive feature;

removing the conformal catalyst layer from the bottom of the line trench and the top of the first conductive feature; and

forming a second conductive feature in the line trench.

9. The method of claim 8, further comprising forming a third conductive feature underlying and in contact with the first conductive feature.

10. The method of claim 9, wherein the third conductive feature comprises silicide.

11. The method of claim 9, wherein the third conductive feature comprises copper.

12. The method of claim 8, wherein the forming the first conductive feature comprises forming carbon nanotubes (CNTs) by a chemical vapor deposition (CVD) operation.

13. The method of claim 8, wherein the forming the second conductive feature comprises forming graphene by a CVD operation.

14. The method of claim 8, wherein the removing the conformal catalyst layer comprises performing an anisotropic etch.

15. The method of claim 8, wherein the forming the conformal catalyst layer comprises depositing Fe, Co, Ni, Cu or alloys thereof.

16. A method for manufacturing an interconnect structure, comprising:

forming a via opening having a first aspect ratio in a first dielectric layer;

forming a line trench having a second aspect ratio over the via opening in a second dielectric layer, the first aspect ratio being equivalent to or greater than the second aspect ratio;

forming a first conductive feature in the via opening after forming the via opening in the first dielectric layer and the line trench in the second dielectric layer;

forming a conformal catalyst layer over the line trench, a bottom of the line trench, and a top of the first conductive feature;

removing the conformal catalyst layer from the bottom of the line trench and the top of the first conductive feature; and

forming a second conductive feature in the line trench.

17. The method of claim 16, further comprising:

forming a first barrier layer between the first dielectric layer and the first conductive feature; and

forming a second barrier layer between the second dielectric layer and the second conductive feature.

18. The method of claim 17, wherein the first barrier layer and the second barrier layer comprise Ta, TaN, TiN, or combinations thereof.

19. The method of claim 18, further comprising forming a ruthenium (Ru)-containing layer between the second conductive feature and the second barrier layer.

20. The method of claim 16, further comprising forming a third conductive feature underlying and in contact with the first conductive feature in a third dielectric layer.