Hardware-adaptable watermark systems

• US 9,819,950 B2
• Filed: 09/01/2015
• Issued: 11/14/2017
• Est. Priority Date: 07/02/2015
• Status: Active Grant

• Current Assignee: Digimarc Corporation
• Original Assignee: Digimarc Corporation
• Inventors: Boles, Jacob L., Sharma, Ravi K., Lord, John D.
• Primary Examiner(s): AZARIAN, SEYED H
• Application Number:
  US14/842,575
• Publication Number:
  US 20170004597A1
• Time in Patent Office: 805 Days
• Field of Search: 382100, 382103, 382162, 382168, 382173, 382181, 382232, 382235, 382243, 382254, 382276, 382286-287, 382305, 704500, 713176, 235468
• CPC Class Codes: G06T 1/005 Robust watermarking, e.g. average attack or collusion attack resistant
• CPC Class Codes: G06T 1/0064 Geometric transfor invariant watermarking, e.g. affine transform invariant
• CPC Class Codes: G06T 2200/08 involving all processing steps from image acquisition to 3D model generation
• CPC Class Codes: G06T 2200/28 involving image processing hardware
• CPC Class Codes: G06T 2201/0065 Extraction of an embedded watermark; Reliable detection
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/467 characterised by the embedded information being invisible, e.g. watermarking

Abstract

There are many advantages to implementing a watermark-based system using dedicated hardware, rather than using software executing on a general purpose processor. These include higher speed and lower power consumption. However, hardware implementations incur substantial design and development costs. Moreover, because each watermarking application has its own design constraints and parameters, it has not been cost-effective to develop a hardware chip design for each, since such chips would typically not be manufactured in volumes sufficient to bring per-unit costs down to an acceptable level. The present technology provides various techniques for making watermarking hardware adaptable, so that a single chip can serve multiple diverse watermark applications. By so-doing, the advantages of hardware implementation are made available where it was formerly cost-prohibitive, thereby enhancing operation of a great variety of watermark-based systems.

Claims

1. A watermark decoder comprising:

a synchronization portion; and

a decoding portion;

at least one of said portions being implemented using hardware circuitry that was designed and fabricated to form part of a watermark decoder, said at least one portion including first means for re-parameterizing one or more facets of its operation to permit customization of said portion, either at a time when the decoder is built, or after it has been placed into service, said first means comprising an application-specific instruction set processor, a cross-bar interconnect, and a memory, the memory being controlled to issue a timed sequence of on/off instructions to plural cross-bar junctions in said cross-bar interconnect.

2. The watermark decoder of claim 1 in which said first means comprises a hardware register that is writable by register control circuitry.

3. The watermark decoder of claim 1 wherein said at least one portion includes first means for re-parameterizing one or more facets of its operation to permit customization of said portion, at a time when the decoder is built, said first means including ROM on a common substrate with said portion, said ROM having been burned to define said customization.

4. The watermark decoder of claim 1 that further includes an image standardization portion, said image standardization portion being implemented using hardware circuitry that was designed and fabricated to form part of a watermark decoder, said image standardization portion including second means for re-parameterizing one or more facets of its operation to permit customization of said portion, either at a time when the decoder is built, or after it has been placed into service.

5. The method of claim 1 wherein said first means comprises means for re-parameterizing one or more facets of its operation by changing at least one of the following parameters:

image size, watermark block size, expected illumination, forward error correction coding algorithm, a number of trial seeds for iterative-based search methods, iteration counts, and watermark reference signals.

6. Apparatus including two watermark decoders according to claim 1, wherein a first of said watermark decoders is incorporated into a first device selected from the list consisting of:

a point of sale scanner for a supermarket checkout, a handheld scanner, a smartphone watermark detector, and an age verification terminal, and a second of said watermark decoders is incorporated into a second device selected from said list, wherein the second device is different than the first device.

7. The watermark decoder of claim 1 wherein said first means is for re-parameterizing said one or more facets of its operation to permit customization of said portion at a time when the decoder is built.

8. The watermark decoder of claim 1 wherein said first means is for re-parameterizing said one or more facets of its operation to permit customization of said portion after it has been placed into service.

9. The watermark decoder of claim 1 wherein said first means forms part of the synchronization portion.

10. The watermark decoder of claim 1 wherein said first means forms part of the decoding portion.

11. A watermark decoder comprising:

a synchronization portion; and

a decoding portion;

at least one of said portions being implemented using hardware circuitry that was designed and fabricated to form part of a watermark decoder, said at least one portion including first means for re-parameterizing one or more facets of its operation to permit customization of said portion, either at a time when the decoder is built, or after it has been placed into service;

the watermark decoder further including a series of pipelined modules, wherein the first means includes data packet intercept control logic that selectively intercepts data output from one pipelined module in said series, and passes the intercepted data to a processor for additional processing that yields a processed data packet, before re-introducing said processed data packet to an input of a subsequent one of said plural pipelined modules.

12. The watermark decoder of claim 11 in which said data packet intercept control logic comprises MUX/DEMUX logic circuitry.

13. A watermark decoder comprising:

a synchronization portion; and

a decoding portion;

at least one of said portions being implemented using hardware circuitry that was designed and fabricated to form part of a watermark decoder, said at least one portion including first means for re-parameterizing one or more facets of its operation to permit customization of said portion, either at a time when the decoder is built, or after it has been placed into service;

the watermark decoder further including an image standardization portion, said image standardization portion being implemented using hardware circuitry that was designed and fabricated to form part of a watermark decoder, said image standardization portion including second means for re-parameterizing one or more facets of its operation to permit customization of said portion, either at a time when the decoder is built, or after it has been placed into service;

the watermark decoder also including a series of pipelined modules, wherein;

the first means comprises at least one of;

(a) a hardware register that is writable by register control circuitry;

(b) an application-specific instruction set processor, a cross-bar interconnect, and a memory, the memory being controlled to issue a timed sequence of on/off instructions to plural cross-bar junctions in said cross-bar interconnect; and

(c) data packet intercept control logic that selectively intercepts data output from one pipelined module in said series, and passes the intercepted data to a processor for additional processing that yields a processed data packet, before re-introducing said processed data packet to an input of a subsequent one of said plural pipelined modules; and

the second means comprises at least one of the foregoing (a), (b) or (c); and

the watermark decoder includes;

at least (a) and (b), or (a) and (c), or (b) and (c).

14. A method comprising the acts:

obtaining first and second identical watermark decoder chips, said chips each including a synchronization portion and a decoding portion, said chips each having been designed and fabricated to form part of a watermark decoder;

parameterizing the first watermark decoder chip to serve in a first application; and

parameterizing the second watermark decoder chip to serve in a second application;

wherein at least one of the following parameters is different between the first and second applications;

image size, watermark block size, expected illumination, forward error correction coding algorithm, a number of trial seeds for iterative-based search methods, iteration counts, and watermark reference signals.

15. The method of claim 14 in which the first application is selected from the list consisting of:

a point of sale scanner for a supermarket checkout, a handheld scanner, a smartphone watermark detector, and an age verification terminal.

16. The method of claim 15 in which the second application is also selected from said list.

17. A method employing a watermark decoder chip, said chip including a synchronization portion and a decoding portion, said chip having been designed and fabricated to form part of a watermark decoder, the method comprising the acts;

(a) parameterizing said watermark decoder chip with first parameters to enable the chip to decode watermarks of a first type; and

(b) plural months after performing act (a), parameterizing said watermark decoder chip with second parameters to enable the chip to decode watermarks of a second type different than the first type;

wherein watermarks of said second type would have been undecodable when the watermark decoder chip was parameterized with said first parameters.

18. The method of claim 17 in which said first and second parameters are different concerning at least one of:

image size, watermark block size, expected illumination, forward error correction coding algorithm, a number of trial seeds for iterative-based search methods, iteration counts, and watermark reference signals.

19. A watermark decoder comprising:

an image standardization portion;

a synchronization portion; and

a decoding portion;

at least one of said synchronization or decoding portion being implemented using hardware circuitry that was designed and fabricated to form part of a watermark decoder, said at least one synchronization or decoding portion including first means for re-parameterizing one or more facets of its operation to permit customization of said portion, either at a time when the decoder is built, or after it has been placed into service;

at least said image standardization portion being implemented using hardware circuitry that was designed and fabricated to form part of a watermark decoder, said image standardization portion including second means for re-parameterizing one or more facets of its operation to permit customization of said portion, either at a time when the decoder is built, or after it has been placed into service.

20. The watermark decoder of claim 19 in which said second means comprises an ASIP processor, a cross-bar interconnect, and a memory, the memory being controlled to issue a timed sequence of on/off instructions to plural cross-bar junctions in said cross-bar interconnect.

21. The watermark decoder of claim 19 in which said second means comprises a hardware register that is writable by register control circuitry.

22. The watermark decoder of claim 19 wherein said image standardization portion includes a ROM that has been burned to define said customization.

23. The method of claim 19 wherein said second means comprises means for re-parameterizing one or more facets of its operation by changing at least one of the following parameters:

image size, watermark block size, expected illumination, forward error correction coding algorithm, a number of trial seeds for iterative-based search methods, iteration counts, and watermark reference signals.

24. The watermark decoder of claim 19 wherein said second means is for re-parameterizing said one or more facets of its operation to permit customization of said portion at a time when the decoder is built.

25. The watermark decoder of claim 19 wherein said second means is for re-parameterizing said one or more facets of its operation to permit customization of said portion after it has been placed into service.