Current-controlled CMOS logic family

• US 9,831,853 B2
• Filed: 08/14/2015
• Issued: 11/28/2017
• Est. Priority Date: 06/28/1999
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Hairapetian, Armond
• Primary Examiner(s): Nguyen, Hai L
• Application Number:
  US14/826,557
• Publication Number:
  US 20150349769A1
• Time in Patent Office: 837 Days
• CPC Class Codes: H03K 17/04 Modifications for accelerating switching
• CPC Class Codes: H03K 17/04106 in field-effect transistor switches H03K17/0412, H03K17/0416 take precedence
• CPC Class Codes: H03K 17/04163 in field-effect transistor switches
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 19/09432 with coupled sources or source coupled logic H03K19/096 takes precedence
• CPC Class Codes: H03K 19/215 using field-effect transistors
• CPC Class Codes: H03K 2217/0036 Means reducing energy consumption
• CPC Class Codes: H03K 3/356043 with synchronous operation
• CPC Class Codes: H03K 3/356139 with synchronous operation
• CPC Class Codes: H03K 3/3562 of the master-slave type

Abstract

Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C³MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C³MOS techniques. Optimum balance between power consumption and speed for each circuit application is achieve by combining high speed C³MOS logic with low power conventional CMOS logic. The combined C³MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Claims

1. An apparatus comprising:

an integrated circuitry, including conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current being dissipated and including current-controlled complementary metal-oxide semiconductor (C³MOS) logic, configured to deserialize a serialized signal to generate a plurality of signals; and

wherein;

the C³MOS logic including a first metal-oxide semiconductor (MOS) transistor with a first drain, a first gate, and a first source and a second MOS transistor with a second drain, a second gate, and a second source, wherein;

a current steering circuit within the C³MOS logic including the first source and the second source;

the first source and the second source being coupled together and to a current source;

the first drain and the second drain being coupled to a power supply; and

the first gate and the second gate configured to receive a first differential signal and the first drain and the second drain configured to output a second differential signal in accordance with deserializing the serialized signal to generate the plurality of signals.

2. The apparatus of claim 1 further comprising:

a C³MOS logic circuitry, within the integrated circuitry, configured to receive the serialized signal and to generate the plurality of signals; and

a CMOS logic circuitry, within the integrated circuitry, configured to receive at least one of the plurality of signals from the C³MOS logic circuitry.

3. The apparatus of claim 1 further comprising:

a C³MOS logic circuitry, within the integrated circuitry, configured to receive the serialized signal and to generate the plurality of signals; and

a first CMOS logic circuitry, within the integrated circuitry, configured to receive a first signal of the plurality of signals from the C³MOS logic circuitry; and

a second CMOS logic circuitry, within the integrated circuitry, configured to receive a second signal of the plurality of signals from the C³MOS logic circuitry.

4. The apparatus of claim 1 further comprising:

a first C³MOS logic circuitry, within the integrated circuitry, configured to receive the serialized signal and to generate the plurality of signals; and

a CMOS logic circuitry, within the integrated circuitry, configured to process the plurality of signals to generate a plurality of processed signals; and

a second C³MOS logic circuitry configured to receive the plurality of processed signals.

5. The apparatus of claim 1, wherein the CMOS logic is further configured to operate as an inverter, a buffer, a level shifter, an AND gate, a NAND gate, an OR gate, a NOR gate, an XOR gate, a latch, or a flip-flop.

6. The apparatus of claim 1, wherein:

the serialized signal has a first frequency; and

each signal of the plurality of signals has a second frequency that is different than the first frequency.

7. The apparatus of claim 1, wherein:

the serialized signal has a first frequency; and

each signal of the plurality of signals has a second frequency that is approximately one-half of the first frequency.

8. The apparatus of claim 1 further comprising:

a C³MOS logic circuitry, within the integrated circuitry, coupled to a first power supply voltage; and

a CMOS logic circuitry, within the integrated circuitry, coupled to a second power supply voltage that is different than the first power supply voltage.

9. The apparatus of claim 1, wherein the plurality of signals and the serialized signal being electrical signals including data compliant with a fiber channel.

10. The apparatus of claim 1, wherein the serialized signal being a differential signal.

11. An apparatus comprising:

an integrated circuitry, including conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current being dissipated and including current-controlled complementary metal-oxide semiconductor (C³MOS) logic, configured to;

receive a first serialized signal;

process the first serialized signal to generate a second serialized signal; and

output the second serialized signal; and

wherein;

the C³MOS logic including a first metal-oxide semiconductor (MOS) transistor with a first drain, a first gate, and a first source and a second MOS transistor with a second drain, a second gate, and a second source, wherein;

a current steering circuit within the C³MOS logic including the first source and the second source;

the first source and the second source being coupled together and to a current source;

the first drain and the second drain being coupled to a power supply; and

the first gate and the second gate configured to receive a first differential signal and the first drain and the second drain configured to output a second differential signal in accordance with receiving the first serialized signal, processing the first serialized signal to generate the second serialized signal, or outputting the second serialized signal.

12. The apparatus of claim 11 further comprising:

a first C³MOS logic circuitry, within the integrated circuitry, configured to process the first serialized signal to generate a plurality of signals; and

a CMOS logic circuitry, within the integrated circuitry, configured to process the plurality of signals to generate a plurality of processed signals, wherein each signal of the plurality of signals and the plurality of processed signals has a first frequency; and

a second C³MOS logic circuitry configured to process the plurality of processed signals to generate the second serialized signal, wherein the first serialized signal and the second serialized signal have a second frequency that is different than the first frequency.

13. The apparatus of claim 11, wherein the C³MOS logic is further configured to operate as an inverter, a buffer, a level shifter, an AND gate, a NAND gate, an OR gate, a NOR gate, an XOR gate, a latch, or a flip-flop.

14. The apparatus of claim 11 further comprising:

a C³MOS logic circuitry, within the integrated circuitry, coupled to a first power supply voltage; and

a CMOS logic circuitry, within the integrated circuitry, coupled to a second power supply voltage that is different than the first power supply voltage.

15. The apparatus of claim 11, wherein the first serialized signal of the second serialized signal being an electrical signal including data compliant with a fiber channel.

16. An apparatus comprising:

an integrated circuitry, including conventional complementary metal-oxide-semiconductor (CMOS) logic wherein substantially zero static current being dissipated and including current-controlled complementary metal-oxide semiconductor (C³MOS) logic, configured to process a first signal using at least one processing operation to generate a second signal, wherein the at least one processing operation corresponds to an inverter, a buffer, a level shifter, an AND gate, a NAND gate, an OR gate, a NOR gate, an XOR gate, a latch, or a flip-flop; and

wherein;

the C³MOS logic including a first metal-oxide semiconductor (MOS) transistor with a first drain, a first gate, and a first source and a second MOS transistor with a second drain, a second gate, and a second source, wherein;

a current steering circuit within the C³MOS logic including the first source and the second source;

the first source and the second source being coupled together and to a current source;

the first drain and the second drain being coupled to a power supply; and

the first gate and the second gate configured to receive a first differential signal and the first drain and the second drain configured to output a second differential signal in accordance with processing the first signal using at least one processing operation to generate the second signal.

17. The apparatus of claim 16 further comprising:

a C³MOS logic circuitry, within the integrated circuitry, configured to receive the first signal and to generate another signal; and

a CMOS logic circuitry, within the integrated circuitry, configured to process the another signal to generate the second signal.

18. The apparatus of claim 16, wherein at least one of the first signal or the second signal including data compliant with a fiber channel.

19. The apparatus of claim 16 further comprising:

a C³MOS logic circuitry, within the integrated circuitry, coupled to a first power supply voltage; and

a CMOS logic circuitry, within the integrated circuitry, coupled to a second power supply voltage that is different than the first power supply voltage.

20. The apparatus of claim 16, wherein the first signal or the second signal being a differential signal.