Imaging sensor and imaging device with column ADC

• US 9,832,408 B2
• Filed: 12/04/2014
• Issued: 11/28/2017
• Est. Priority Date: 06/08/2012
• Status: Active Grant

• Current Assignee: Nikon Corporation
• Original Assignee: Nikon Corporation
• Inventors: Murata, Hironobu
• Primary Examiner(s): Ye, Lin
• Assistant Examiner(s): Morehead, III, John H
• Application Number:
  US14/560,710
• Publication Number:
  US 20150163441A1
• Time in Patent Office: 1,090 Days
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H04N 25/70 SSIS architectures; Circuits associated therewith
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• CPC Class Codes: H04N 25/772 comprising A/D, V/T, V/F, I/T or I/F converters

Abstract

An imaging sensor comprising: an imaging chip in which a plurality of pixel are arranged in a matrix; and a signal processing chip that is each provided for one or more pixel columns or one or more pixel rows, has a device that performs signal processing on a pixel signal output from a pixel, and is stacked with the imaging chip is provided. For example, the device that performs signal processing is an A/D converter that converts a pixel signal output from the pixel into a digital signal, and when a pixel signal output from the pixel is converted into a digital signal, at least two or more A/D converters among the A/D converters are controlled in parallel.

Claims

1. An imaging sensor comprising:

an imaging chip having

a pixel unit that has first and second pixel regions that each includes a plurality of pixels,

a readout unit that is provided for each of the first and second pixel regions, and each readout unit reading out signals from pixels of each of the first and second pixel regions, and

a signal line that is provided for each of the first and second pixel regions; and

a signal processing chip above which the imaging chip is stacked, the signal processing chip having

a signal processing unit that is stacked with the pixel unit and has (i) a first signal processing circuit that performs signal processing on a signal from a first pixel of the first pixel region that is read out by the readout unit for the first pixel region and output to the first signal processing circuit via the signal line for the first pixel region, and (ii) a second signal processing circuit that performs signal processing on a signal from a second pixel of the second pixel region that is read out by the readout unit for the second pixel region and output to the second signal processing circuit via the signal line for the second pixel region,

both the first pixel region and the second pixel region being stacked above both the first signal processing circuit and the second signal processing circuit such that both the first pixel region and the second pixel region overlap both the first signal processing circuit and the second signal processing circuit as viewed along a direction parallel to an optical axis of the imaging sensor, and

the first pixel region being connected to only the first signal processing circuit, and the second pixel region being connected to only the second signal processing circuit.

2. The imaging sensor according to claim 1, wherein

the first signal processing circuit includes a first A/D converter that converts a pixel signal from the first pixel into a digital signal, and

the second signal processing circuit includes a second A/D converter that converts a pixel signal from the second pixel into a digital signal.

3. The imaging sensor according to claim 1, wherein

the pixel unit and the signal processing unit are connected via a plurality of bumps, and

the bumps are arranged in the first and second pixel regions respectively.

4. The imaging sensor according to claim 1, wherein

the pixel unit and the signal processing unit are connected via a plurality of bumps, and

the plurality of bumps are arranged at constant intervals.

9. The imaging sensor according to claim 1, wherein

the first pixel region is arranged as a first column of pixels, and the second pixel region is arranged as a second column of pixels.

5. An imaging sensor comprising:

an imaging chip having

a pixel unit that has first and second pixel regions that each includes a plurality of pixels,

a readout unit that is provided for each of the first and second pixel regions, each readout unit reading out signals from pixels of each of the first and second pixel regions, and

a signal line that is provided for each of the first and second pixel regions; and

a signal processing chip above which the imaging chip is stacked, the signal processing chip having

a signal processing unit that is stacked with the pixel unit and has (i) a first signal processing circuit that performs signal processing on a signal from a first pixel of the first pixel region and a signal from a second pixel of the first pixel region, that are read out by the readout unit for the first pixel region and output to the first signal processing circuit via the signal line for the first pixel region, and (ii) a second signal processing circuit that performs signal processing on a signal from a third pixel of the second pixel region and a signal from a fourth pixel of the second pixel region, that are read out by the readout unit for the second pixel region and output to the second signal processing circuit via the signal line for the second pixel region,

both the first pixel region and the second pixel region being stacked above both the first signal processing circuit and the second signal processing circuit such that both the first pixel region and the second pixel region overlap both the first signal processing circuit and the second signal processing circuit as viewed along a direction parallel to an optical axis of the imaging sensor, and

the first pixel region being connected to only the first signal processing circuit, and the second pixel region being connected to only the second signal processing circuit.

6. The imaging sensor according to claim 5, wherein

the first signal processing circuit includes a first A/D converter that converts the signal from the first pixel and the signal from the second pixel into a digital signal, and

the second signal processing circuit includes a second A/D converter that converts the signal from the third pixel and the signal from the fourth pixel into a digital signal.

7. The imaging sensor according to claim 5, wherein

the pixel unit and the signal processing unit are connected via a plurality of bumps, and

each bump is arranged in a respective one of the first and second pixel regions.

8. The imaging sensor according to claim 5, wherein

the pixel unit and the signal processing unit are connected via a plurality of bumps arranged at constant intervals.

10. The imaging sensor according to claim 5, wherein

the first pixel region is arranged as a first column of pixels, and the second pixel region is arranged as a second column of pixels.