Panel level fabrication of package substrates with integrated stiffeners

• US 9,832,860 B2
• Filed: 09/26/2014
• Issued: 11/28/2017
• Est. Priority Date: 09/26/2014
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Starkston, Robert, Guzek, John, Nardi, Patrick, Jones, Keith, Soto Gonzalez, Javier
• Primary Examiner(s): Van Roy, Tod T
• Assistant Examiner(s): FORDE, DELMA ROSA
• Application Number:
  US14/498,958
• Publication Number:
  US 20160095209A1
• Time in Patent Office: 1,159 Days
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 23/16 Fillings or auxiliary members in containers or encapsulations, e.g. centering rings H01L23/42, H01L23/552 take precedence
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/562 Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/351 Thermal stress
• CPC Class Codes: H05K 1/0271 Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
• CPC Class Codes: H05K 2201/09136 Means for correcting warpage
• CPC Class Codes: H05K 2201/10977 Encapsulated connections applying non-metallic protective coatings for encapsulating mounted components H05K3/284
• CPC Class Codes: H05K 2201/2009 Reinforced areas, e.g. for a specific part of a flexible printed circuit
• CPC Class Codes: H05K 3/0052 Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards
• CPC Class Codes: H05K 3/0097 Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards H05K3/0052 takes precedence
• CPC Class Codes: H05K 3/284 for encapsulating mounted components H05K1/185 takes precedence

Abstract

Techniques are disclosed for forming a package substrate with integrated stiffener. A panel of package substrates are provided. An adhesion layer is then formed on each package substrate of the panel of package substrates. A panel of stiffeners are then attached to the panel of package substrates by the adhesion layer, each stiffener corresponding to a respective package substrate. The panel of package substrates is then singulated into individual package substrates with integrated stiffeners. The stiffeners on the singulated package substrates include tabs that extend to the edges of the package substrates.

Claims

1. A package substrate, comprising:

a substrate having a first plurality of pads on a first surface and a second plurality of pads on a second surface opposite of the first surface;

an adhesion layer disposed on the first surface and around the first plurality of pads; and

a stiffener disposed on top of the adhesion layer and around the first plurality of pads, the stiffener having a tab comprising a first portion of an outer edge of the stiffener that extends to an edge of the substrate, the tab having a length extending along a portion of the edge of the substrate, wherein a second portion of the outer edge of the stiffener does not extend to the edge of the substrate.

2. The package substrate of claim 1, wherein the first portion of the outer edge of the stiffener is located on a side of the stiffener.

3. The package substrate of claim 1, wherein the first portion of the outer edge of the stiffener is located at a corner of the stiffener.

4. The package substrate of claim 1, wherein the stiffener is formed of a metal.

5. A device package, comprising:

a substrate having a first plurality of pads on a first surface and a second plurality of pads on a second surface opposite of the first surface;

a semiconductor die coupled to the first plurality of pads;

a second level interconnect (SLI) structure coupled to the second plurality of pads;

an adhesion layer disposed on the first surface and around the first plurality of pads and the semiconductor die; and

a stiffener disposed on top of the adhesion layer and around the first plurality of pads and the semiconductor die, the stiffener having a tab comprising a first portion of an outer edge of the stiffener that extends to an edge of the substrate, the tab having a length extending along a portion of the edge of the substrate, wherein a second portion of the outer edge of the stiffener does not extend to the edge of the substrate.

6. The device package of claim 5, further comprising an underfill material disposed between the die and the first surface of the substrate.

7. The device package of claim 6, wherein the underfill material contacts an inner edge of the stiffener.

8. The device package of claim 7, further comprising an underfill keep out zone that is a region of the first surface disposed between the inner edge of the stiffener and the first plurality of pads.

9. The device package of claim 8, wherein the distance between the inner edge of the stiffener and the first plurality of pads is less than 2 mm.

10. The device package of claim 7, wherein the underfill material has a planar top surface.

11. The device package of claim 10, wherein the planar top surface of the underfill material is below the top surface of the stiffener.

12. The device package of claim 10, wherein the planar top surface is substantially horizontal.

13. The device package of claim 5, wherein the die extends above the stiffener.

14. The device package of claim 5, wherein the first portion of the outer edge of the stiffener is located on a side of the stiffener.

15. The device package of claim 5, wherein the first portion of the outer edge of the stiffener is located at a corner of the stiffener.