Dynamic cache allocation policy adaptation in a data processing apparatus

• US 9,836,403 B2
• Filed: 05/01/2015
• Issued: 12/05/2017
• Est. Priority Date: 06/05/2014
• Status: Active Grant

• Current Assignee: Arm Limited (SoftBank Group Corp.)
• Original Assignee: Arm Limited (SoftBank Group Corp.)
• Inventors: Johar, Kauser, Penton, Antony John, Hughes, Zemian
• Primary Examiner(s): Faal, Baboucarr
• Application Number:
  US14/702,049
• Publication Number:
  US 20150356019A1
• Time in Patent Office: 949 Days
• Field of Search: None
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/0871 Allocation or management of cache space
• CPC Class Codes: G06F 2212/6046 Using a specific cache allocation policy other than replacement policy
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device

Abstract

A data processing apparatus and method of processing data are disclosed according to which a processor unit is configured to issue write access requests for memory which are buffered and handled by a memory access buffer. A cache unit is configured, in dependence on an allocation policy defined for the cache unit, to cache accessed data items. Memory transactions are constrained to be carried out so that all of a predetermined range of memory addresses within which one or more memory addresses specified by the buffered write access requests lie must be written by the corresponding write operation. If the buffered write access requests do not comprise all memory addresses within at least two predetermined ranges of memory addresses, and the cache unit is configured to operate with a no-write allocate policy, the data processing apparatus is configured to cause the cache unit to subsequently operate with a write allocate policy.

Claims

1. A data processing apparatus comprising:

a processor configured to issue a write access request which specifies a memory address and a data item in order to cause the data item to be stored in a memory at the memory address;

a cache memory configured, in dependence on an allocation policy defined for the cache memory, to store a local copy of an accessed data item from the memory for subsequent access by the processor; and

a memory access buffer configured to buffer one or more write access requests issued by the processor until a memory transaction trigger condition is satisfied and then to cause a memory transaction with respect to the memory to be initiated which comprises carrying out the one or more buffered write access requests,

wherein the memory transaction is constrained to carry out a write operation in which all of a predetermined range of memory addresses within which one or more memory addresses specified by the one or more buffered write access requests lies are written by the write operation,

wherein the data processing apparatus is configured to identify an access undersize condition when the buffered write access requests do not comprise all memory addresses within at least two predetermined ranges of memory addresses, and

when the cache memory is configured to operate with the allocation policy as a no-write allocate policy according to which the local copy of the accessed data item is not stored in the cache memory and the access undersize condition is met, the data processing apparatus is configured to cause the cache memory to subsequently operate with the allocation policy as a write allocate policy according to which the local copy of the accessed data item is stored in the cache memory.

2. The data processing apparatus as claimed in claim 1, wherein the cache memory is configured to operate in a write-through mode according to which modification of the local copy of the accessed data item by the subsequent access also causes modification of a corresponding original data item in the memory.

3. The data processing apparatus as claimed in claim 1, wherein the memory access buffer is configured, when the one or more buffered write access requests for which the memory access transaction is to be carried out specify memory addresses in at least one predetermined range of memory addresses which do not comprise all memory addresses within the at least one predetermined range of memory addresses, to cause the memory access transaction to comprise retrieving at least one extended data item indicated by the at least one predetermined range of memory addresses, causing the one or more data items specified in the buffered write access requests to be merged into the retrieved at least one extended data item, and writing the modified at least one extended data item back to the memory.

4. The data processing apparatus as claimed in claim 1, wherein the data processing apparatus is configured, after causing the cache memory to subsequently operate with the allocation policy as the write allocate policy, and when the memory transaction trigger condition is satisfied, to identify an access full-size condition when the buffered write access requests for which a memory access transaction is to be carried out specify memory addresses which comprise all memory addresses in at least one predetermined range of memory addresses within which the specified memory addresses lie, and when the access full-size condition is met, the memory access buffer is configured to cause the cache memory to switch back to operation with the allocation policy as the no-write allocate policy.

5. The data processing apparatus as claimed in claim 1, wherein the cache memory is configured initially to operate with the allocation policy as the no-write allocate policy.

6. The data processing apparatus as claimed in claim 1, wherein data items are stored in the memory with associated error correction code and the predetermined range of memory addresses is determined by a unit data item size which must be read from the memory in order for the associated error correction code to be updated.

7. The data processing apparatus as claimed in claim 6, further comprising an error correction code determination circuitry configured to determine updated error correction code values for inclusion in the memory transaction.

8. The data processing apparatus as claimed in claim 7, wherein the memory access buffer comprises the error correction code determination circuitry.

9. The data processing apparatus as claimed in claim 1, wherein the predetermined range of memory addresses is determined by a unit data size for the memory transaction with respect to the memory.

10. The data processing apparatus as claimed in claim 1, wherein the memory access buffer comprises an access slot, wherein the access slot is configured to buffer write access requests issued by the processor with respect to a selected memory address stored in association with the access slot.

11. The data processing apparatus as claimed in claim 10, wherein the access slot is configured to have a size which is less than the cache line size.

12. The data processing apparatus as claimed in claim 1, wherein the memory access buffer comprises multiple access slots, wherein each access slot is configured to buffer write access requests issued by the processor with respect to a selected memory address stored in association with that access slot.

13. The data processing apparatus as claimed in claim 12, wherein the data processing apparatus is configured to identify the access undersize condition with respect to the multiple write access requests which are buffered in more than one access slot.

14. The data processing apparatus as claimed in claim 1, wherein the data processing apparatus is configured to identify the access undersize condition when the buffered write requests which do not comprise all memory addresses within at least two predetermined ranges of memory addresses are carried out in a single memory transaction.

15. The data processing apparatus as claimed in claim 12, wherein the memory access buffer is configured to identify the access undersize condition when the buffered write requests which do not comprise all memory addresses within at least two predetermined ranges of memory addresses are carried out in separate memory transactions which are carried out at less than a predetermined separation from one another.

16. The data processing apparatus as claimed in claim 15, wherein the separate memory transactions are carried out back-to-back with respect to one another.

17. The data processing apparatus as claimed in claim 1, wherein the memory access buffer is configured to identify the access undersize condition, and the memory access buffer is configured to cause the cache memory to change allocation policy in dependence on the access undersize condition.

18. A method of data processing comprising the steps of:

issuing a write access request which specifies a memory address and a data item in order to cause the data item to be stored in a memory at the memory address;

in dependence on an allocation policy, storing a local copy of an accessed data item from the memory for subsequent access;

buffering one or more write access requests that have been issued until a memory transaction trigger condition is satisfied and then causing a memory transaction with respect to the memory to be initiated which comprises carrying out the one or more buffered write access requests,

wherein the memory transaction is constrained to carry out a write operation in which all of a predetermined range of memory addresses within which one or more memory addresses specified by the one or more buffered write access requests lies are written by the write operation;

identifying an access undersize condition when the buffered write access requests do not comprise all memory addresses within at least two predetermined ranges of memory addresses; and

when the allocation policy is a no-write allocate policy according to which the local copy of the accessed data item is not stored and the access undersize condition is met, causing the allocation policy to change to a write allocate policy according to which the local copy of the accessed data item is stored.

19. A data processing apparatus comprising:

means for issuing a write access request which specifies a memory address and a data item in order to cause the data item to be stored in a memory at the memory address;

means for storing, in dependence on an allocation policy, a local copy of an accessed data item from the memory for subsequent access;

means for buffering one or more write access requests that have been issued by the means for issuing until a memory transaction trigger condition is satisfied and then causing a memory transaction with respect to the memory to be initiated which comprises carrying out the one or more buffered write access requests, wherein the memory transaction is constrained to carry out a write operation in which all of a predetermined range of memory addresses within which one or more memory addresses specified by the one or more buffered write access requests lies are written by the write operation;

means for identifying an access undersize condition when the buffered write access requests do not comprise all memory addresses within at least two predetermined ranges of memory addresses; and

means for, when the allocation policy is a no-write allocate policy according to which the local copy of the accessed data item is not stored and the access undersize condition is met, causing the allocation policy to change to a write allocate policy according to which the local copy of the accessed data item is stored.