Gate drivers for stacked transistor amplifiers

  • US 9,843,293 B1
  • Filed: 09/16/2016
  • Issued: 12/12/2017
  • Est. Priority Date: 09/16/2016
  • Status: Active Grant
First Claim
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1. A circuital arrangement comprising:

  • a transistor stack configured to operate as an amplifier, the transistor stack comprising a plurality of stacked transistors comprising an input transistor and an output transistor;

    the transistor stack configured to operate between a first supply voltage coupled to the output transistor and a reference voltage coupled to the input transistor;

    a first resistive ladder network comprising a plurality of series connected resistors coupled between a second supply voltage and the reference voltage, the resistive ladder network defining low impedance gate bias voltage nodes between any two connected resistors of the first series connected resistors;

    a second resistive ladder network comprising a plurality of series connected resistors coupled between the second supply voltage and the reference voltage, the resistive ladder network defining high impedance gate bias voltage nodes between any two connected resistors of the second series connected resistors; and

    one or more switches configured to selectively couple one of the low impedance gate bias voltage nodes and the high impedance gate bias voltage nodes to gates of transistors of the plurality of stacked transistors except the input transistor.

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