Gate drivers for stacked transistor amplifiers
First Claim
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1. A circuital arrangement comprising:
- a transistor stack configured to operate as an amplifier, the transistor stack comprising a plurality of stacked transistors comprising an input transistor and an output transistor;
the transistor stack configured to operate between a first supply voltage coupled to the output transistor and a reference voltage coupled to the input transistor;
a first resistive ladder network comprising a plurality of series connected resistors coupled between a second supply voltage and the reference voltage, the resistive ladder network defining low impedance gate bias voltage nodes between any two connected resistors of the first series connected resistors;
a second resistive ladder network comprising a plurality of series connected resistors coupled between the second supply voltage and the reference voltage, the resistive ladder network defining high impedance gate bias voltage nodes between any two connected resistors of the second series connected resistors; and
one or more switches configured to selectively couple one of the low impedance gate bias voltage nodes and the high impedance gate bias voltage nodes to gates of transistors of the plurality of stacked transistors except the input transistor.
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Abstract
Various methods and circuital arrangements for biasing one or more gates of stacked transistors of an amplifier are possible where the amplifier is configured to operate in at least an active mode and a standby mode. Circuital arrangements can reduce bias circuit and stacked transistors standby current during operation in the standby mode and to reduce impedance presented to the gates of the stacked transistors during operation in the active mode while maintaining voltage compliance of the stacked transistors during both modes of operation.
64 Citations
26 Claims
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1. A circuital arrangement comprising:
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a transistor stack configured to operate as an amplifier, the transistor stack comprising a plurality of stacked transistors comprising an input transistor and an output transistor;
the transistor stack configured to operate between a first supply voltage coupled to the output transistor and a reference voltage coupled to the input transistor;a first resistive ladder network comprising a plurality of series connected resistors coupled between a second supply voltage and the reference voltage, the resistive ladder network defining low impedance gate bias voltage nodes between any two connected resistors of the first series connected resistors; a second resistive ladder network comprising a plurality of series connected resistors coupled between the second supply voltage and the reference voltage, the resistive ladder network defining high impedance gate bias voltage nodes between any two connected resistors of the second series connected resistors; and one or more switches configured to selectively couple one of the low impedance gate bias voltage nodes and the high impedance gate bias voltage nodes to gates of transistors of the plurality of stacked transistors except the input transistor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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Specification