Semiconductor device

• US 9,847,394 B2
• Filed: 10/12/2016
• Issued: 12/19/2017
• Est. Priority Date: 10/13/2015
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Prechtl, Gerhard, Haeberlen, Oliver, Ostermaier, Clemens
• Primary Examiner(s): Gebreyesus, Yosef
• Application Number:
  US15/291,845
• Publication Number:
  US 20170104076A1
• Time in Patent Office: 433 Days
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/42316 for field-effect transistors
• CPC Class Codes: H01L 29/778 with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface H01L29/803 takes precedence
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
• CPC Class Codes: H01L 29/861 Diodes

Abstract

In an embodiment, a semiconductor device includes a Group III-nitride-based High Electron Mobility Transistor (HEMT) configured as a bidirectional switch. The Group III nitride-based HEMT includes a first input/output electrode, a second input/output electrode, a gate structure arranged between the first input/output electrode and the second input/output electrode, and a field plate structure.

Claims

1. A semiconductor device, comprising:

a Group III-nitride-based High Electron Mobility Transistor (HEMT) configured as a bidirectional switch and comprising a first input/output electrode, a second input/output electrode, a gate structure laterally arranged between the first input/output electrode and the second input/output electrode, and a field plate structure,

wherein the gate structure comprises a horizontal portion that is disposed above a channel of the High Electron Mobility Transistor, and

wherein the field plate structure comprises a horizontal portion that is disposed directly above the horizontal portion of the gate structure and is completely planar across an entire width of the field plate structure.

2. The semiconductor device of claim 1, wherein the field plate structure comprises a vertical portion extending from the horizontal portion, the vertical portion being arranged on and coupled to the gate structure and the horizontal portion of the field plate structure extending substantially symmetrically between the first input/output electrode and the second input/output electrode.

3. The semiconductor device of claim 1, wherein the gate structure comprises a T-shaped gate metal.

4. The semiconductor device of claim 1, wherein the gate structure comprises two independently controllable gates.

5. The semiconductor device of claim 4, wherein the field plate structure comprises a vertical portion arranged between the two independently controllable gates and the horizontal portion of the field plate structure.

6. The semiconductor device of claim 4, wherein the field plate structure comprises a first portion coupled to the first input/output electrode and a second portion coupled to the second input/output electrode.

7. The semiconductor device of claim 1, wherein the Group III-nitride-based HEMT comprises a channel layer comprising GaN and a barrier layer arranged on the channel layer, the barrier layer comprising Al_xGa_(1-x)N, wherein 0<

x<

1.

8. The semiconductor device of claim 1, further comprising at least one p-doped Group III nitride layer under the gate structure.

9. The semiconductor device of claim 1, wherein the field plate structure is arranged asymmetrically with respect to the first input/output electrode and the second input/output electrode.

10. A semiconductor device, comprising:

a Group III-nitride-based High Electron Mobility Transistor (HEMT) configured as a bidirectional switch and comprising a first input/output electrode, a second input/output electrode, a gate structure arranged between the first input/output electrode and the second input/output electrode, a field plate structure, a first diode and a second diode, wherein the first diode and the second diode are coupled anti-serially between the first input/output electrode and the second input/output electrode,

wherein the gate structure comprises a single gate, wherein an anode of the first diode and an anode of the second diode are coupled to a field plate arranged directly over the single gate.

11. The semiconductor device of claim 10, wherein a cathode of the first diode is coupled to the first input/output electrode, and wherein a cathode of the second diode is coupled to the second input/output electrode.

12. The semiconductor device of claim 10, wherein the first diode and the second diode are discrete components.

13. The semiconductor device of claim 10, wherein the first diode and the second diode are integrated into the Group III-nitride-based HEMT.

14. The semiconductor device of claim 13, wherein at least one of the first diode and the second diode comprises an enhancement mode transistor structure comprising a first current electrode, a gate electrode and a second current electrode, wherein the first current electrode is coupled to the gate and to the field plate structure, and wherein the second current electrode is electrically coupled to the first input/output electrode of the Group III-nitride-based HEMT.

15. The semiconductor device of claim 10, wherein at least one of the first diode and the second diode is a pn diode.

16. The semiconductor device of claim 10, wherein the Group III nitride-based HEMT is a depletion mode device.

17. The semiconductor device of claim 10, wherein the Group III-nitride-based HEMT comprises a channel layer comprising GaN and a barrier layer arranged on the channel layer, the barrier layer comprising Al_xGa_(1-x)N, wherein 0<

x<

1.

18. The semiconductor device of claim 17, further comprising at least one p-doped Group III-nitride layer arranged between the gate and the barrier layer.

19. The semiconductor device of claim 18, wherein the p-doped Group III-nitride layer comprises at least one a p-doped GaN layer and a p-doped Al_zGa_(1-z)N layer, wherein 0<

z<

1.

20. The semiconductor device of claim 17, wherein the barrier layer has a laterally thickness and a vertically content.