Method to enhance MIPI D-PHY link rate with minimal PHY changes and no protocol changes

• US 9,853,806 B2
• Filed: 09/12/2016
• Issued: 12/26/2017
• Est. Priority Date: 10/03/2013
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Sengoku, Shoichiro
• Primary Examiner(s): NGUYEN, LEON VIET Q
• Application Number:
  US15/262,280
• Publication Number:
  US 20160380755A1
• Time in Patent Office: 470 Days
• CPC Class Codes: H04L 25/14 Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/0087 Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
• CPC Class Codes: H04L 7/0276 Self-sustaining, e.g. by tuned delay line and a feedback path to a logical gate
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/04 Speed or phase control by synchronisation signals H04L7/0075 takes precedence

Abstract

System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. A first transition may be detected in a signal carried on a data lane of a data communications link or carried on a timing lane of the data communications link and an edge may be generated on a receiver clock signal based on the first transition. Data may be captured from the data lane using the receiver clock signal. The timing lane may carry a clock signal, a strobe signal or another signal providing timing information. The strobe signal may transition between signaling states when no state transition occurs on any of a plurality of data lanes at a boundary between consecutive data periods.

Claims

1. A method of data communications, comprising:

receiving a plurality of data signals from a plurality of data lanes of a data communications link in accordance with a double data rate clock signal received from a timing lane of the data communications link, wherein each transition of the double data rate clock signal is aligned with a boundary between two data periods;

detecting a first-occurring transition on the data communications link at a boundary between a first data period and a second data period, whether the first-occurring transition occurs in a data signal carried on a data lane or in the double data rate clock signal, by comparing signaling state of the data communication link corresponding to the first data period with signaling state of the data communication link corresponding to the second data period;

generating an edge on a receiver clock signal based on the first-occurring transition; and

capturing data received from the plurality of data lanes using the receiver clock signal.

2. The method of claim 1, further comprising:

deserializing data received from one or more data lanes using the receiver clock signal.

3. The method of claim 1, wherein each data lane in the plurality of data lanes is carried on a pair of differentially driven wires.

4. The method of claim 1, and further comprising:

storing a first symbol representative of the signaling state of the data communication link corresponding to the first data period;

and wherein detecting the first-occurring transition comprises;

comparing the first symbol with a second symbol representative of the signaling state of the data communication link corresponding to the second data period,

wherein the first-occurring transition occurs at the transition between the first symbol and the second symbol.

5. The method of claim 4, wherein the first-occurring transition occurs on one of the plurality of data lanes.

6. The method of claim 4, wherein the first-occurring transition occurs in the double data rate clock signal.

7. The method of claim 1, wherein the receiver clock signal is unaffected by one or more additional transitions on the data communications link occurring in relation to the boundary between the first data period and the second data period when the one or more additional transitions occur after the edge has been generated.

8. The method of claim 7, wherein the first data period occurs before the second data period, and wherein the edge is used to capture a delayed version of data transmitted in the first data period.

9. An apparatus, comprising:

a processing circuit configured to;

receive a plurality of data signals from a plurality of data lanes of a data communications link in accordance with a double data rate clock signal received from a timing lane of the data communications link, wherein each transition of the double data rate clock signal is aligned with a boundary between two data periods;

store signaling state of the data communication link corresponding to the first data period;

detect a first-occurring transition on the data communications link at a boundary between a first data period and a second data period, whether the first-occurring transition occurs in a data signal carried on a data lane or in the double data rate clock signal, by comparing the stored signaling state of the data communication link corresponding to the first data period with signaling state of the data communication link corresponding to the second data period;

generate an edge on a receiver clock signal based on the first-occurring transition; and

capture data received from the plurality of data lanes using the receiver clock signal.

10. The apparatus of claim 9, wherein the processing circuit configured to deserialize data received from one or more data lanes using the receiver clock signal.

11. The apparatus of claim 9, wherein the receiver clock signal is unaffected by one or more additional transitions occurring on the data communications link in relation to the boundary between the first data period and the second data period when the one or more additional transitions occur after the edge has been generated.

12. The apparatus of claim 11, wherein the first data period occurs before the second data period, and wherein the edge is used to capture a delayed version of data transmitted in the first data period.

13. The apparatus of claim 9, wherein the first-occurring transition occurs on one of the plurality of data lanes.

14. The apparatus of claim 9, wherein the first-occurring transition occurs in the double data rate clock signal.

15. A clock recovery circuit, comprising:

a plurality of latches configured to store a first signaling state of a plurality of lanes of a data communication link, the plurality of lanes including a timing lane and at least one data lane;

a comparator configured to compare the first signaling state with a second signaling state representing a current signaling state of the plurality of lanes of the data communication link; and

a pulse generation circuit adapted to provide a pulse responsive to a change in output of the comparator corresponding to a first-occurring transition in a double data rate clock signal carried on the timing lane or in a data signal carried in the at least one data lane, wherein each transition of the double data rate clock signal is aligned with a boundary between two data periods of the data signal; and

a clock generation circuit that generates a sampling clock from pulses provided by the pulse generation circuit, the sampling clock being configured to capture data from the at least one data lane,

wherein the plurality of latches replaces the first signaling state with the second signaling state after termination of the pulse.

16. The clock recovery circuit of claim 15, wherein the sampling clock is provided to a deserializer adapted to deserialize a data signal received from one or more lanes of the data communication link.

17. The clock recovery circuit of claim 15, wherein the pulse generation circuit is configured to ignore one or more additional changes in output of the comparator for the duration of the pulse.

18. The clock recovery circuit of claim 17, wherein the first-occurring transition occurs at a boundary between a first data period and a second data period that immediately follows the first data period, and wherein the one or more additional changes in output of the comparator correspond to transitions on the data communication link related to the boundary between the first data period and the second data period.

19. The clock recovery circuit of claim 15, wherein the first-occurring transition occurs at a boundary between a first data period and a second data period that immediately follows the first data period, and wherein the pulse is used to capture a delayed version of data transmitted in the first data period.

20. The clock recovery circuit of claim 15, further comprising:

a plurality of differential receivers configured to provide the second signaling state,

wherein each differential receiver is coupled to one of the plurality of lanes.

21. A clock recovery method, comprising:

storing a first signaling state of a plurality of lanes of a data communication link as a previous signaling state, the plurality of lanes including a timing lane and at least one data lane;

detecting a first-occurring transition in a double data rate clock signal carried on the timing lane or in a data signal carried in the at least one data lane by comparing the previous signaling state with a second signaling state representing a current signaling state of the plurality of lanes of the data communication link, wherein each transition of the double data rate clock signal is aligned with a boundary between two data periods of the data signal; and

generating a pulse when the first-occurring transition is detected;

using the pulse to generate a sampling clock configured to capture data from the at least one data lane; and

storing the second signaling state as the previous signaling state after termination of the pulse.

22. The clock recovery method of claim 21, further comprising:

using the sampling clock to deserialize a data signal received from one or more lanes of the data communication link.

23. The clock recovery method of claim 21, further comprising:

ignoring one or more additional transitions in the plurality of lanes for the duration of the pulse.

24. The clock recovery method of claim 23, wherein the first-occurring transition and the one or more additional transitions occur at a boundary between a first data period and a second data period that immediately follows the first data period.

25. The clock recovery method of claim 21, further comprising:

capturing a delayed version of data transmitted in a first data period, wherein the first-occurring transition occurs at a boundary between the first data period and a second data period that immediately follows the first data period.

26. The clock recovery method of claim 21, wherein the second signaling state is provided by a plurality of differential receivers, and wherein each differential receiver is coupled to one of the plurality of lanes.