Semiconductor device having an airbridge and method of fabricating the same

• US 9,859,205 B2
• Filed: 11/24/2014
• Issued: 01/02/2018
• Est. Priority Date: 01/31/2011
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Whetten, Timothy J., Richling, Wayne P.
• Primary Examiner(s): Arroyo, Teresa M
• Application Number:
  US14/551,492
• Publication Number:
  US 20150102490A1
• Time in Patent Office: 1,135 Days
• Field of Search: 257745, 438605
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/7685 the layer covering a conductive structure H01L21/76849 takes precedence
• CPC Class Codes: H01L 2224/4013 Connecting within a semiconductor or solid-state body, i.e. fly strap, bridge strap
• CPC Class Codes: H01L 2224/4813 Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
• CPC Class Codes: H01L 23/4821 Bridge structure with air gap
• CPC Class Codes: H01L 23/5221 Crossover interconnections
• CPC Class Codes: H01L 23/53252 Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/5381 Crossover interconnections, e.g. bridge stepovers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device and a method of forming an airbridge extending from a conductive area of the semiconductor device are provided. The semiconductor device includes a device pattern formed on a semiconductor substrate, a seed layer formed on the device pattern, and an airbridge formed on the seed layer, where the airbridge includes a plated conductive material and defines an opening exposing a portion of the device pattern. The semiconductor device further includes an adhesion layer formed on the airbridge layer and extending over at least a portion of sidewalls of the opening defined by the airbridge, and an insulating layer formed on the adhesion layer, where the adhesion layer enhances adhesion of the insulating layer to the plated conductive material of the airbridge.

Claims

1. A semiconductor device, comprising:

a device pattern formed on a semiconductor substrate;

a seed layer formed on the device pattern;

an airbridge formed on the seed layer, the airbridge comprising a plated conductive material and defining an opening leading to a corresponding air space in which at least a portion of the device pattern is positioned, the opening being narrower than the corresponding air space, which extends below the airbridge;

an adhesion layer formed on the airbridge and extending over at least a portion of sidewalls of the opening defined by the airbridge; and

an insulating layer formed on the adhesion layer such that the adhesion layer is between the insulating layer and the airbridge, including in the opening defined by the airbridge, enhancing adhesion of the insulating layer to the plated conductive material of the airbridge.

2. The device of claim 1, wherein the plated conductive material comprises gold and the insulating layer comprises silicon nitride.

3. The device of claim 2, wherein the adhesion layer comprises a conductive adhesion material.

4. The device of claim 2, wherein the seed layer comprises plated gold.

5. The device of claim 1, wherein the adhesion layer comprises titanium.

6. The device of claim 1, wherein the adhesion layer comprises tantalum.

7. The device of claim 1, wherein the adhesion layer comprises titanium oxide.

8. The device of claim 1, wherein the semiconductor substrate comprises gallium arsenide (GaAs).

9. The device of claim 8, wherein the semiconductor device comprises one of a monolithic microwave integrated circuit (MMIC), a metal semiconductor field effect transistor (MESFET), a high electron mobility transistor (HEMT), a pseudomorphic high electron mobility transistor (pHEMT), an enhancement-mode pseudomorphic high electron mobility transistor (E-pH EMT), a heterojunction bipolar transistor (HBT).

10. A semiconductor device, comprising:

a transistor formed on a semiconductor substrate, the transistor comprising a gate, a source and a drain;

a first insulating layer formed over the gate, the source and the drain of the transistor;

a conductive seed layer formed on a source electrode connected to the source and on a drain electrode connected to the drain of the transistor;

airbridges formed on the conductive seed layer and extending from each of the source electrode and the drain electrode, the airbridges comprising a conductive material and defining an opening between the airbridges, the opening leading to a corresponding airspace in which at least a portion of the transistor is positioned;

a second insulating layer formed over outer surfaces of the airbridges, including sidewalls of the opening, and further formed on the first insulating layer; and

an adhesion layer formed between a portion of each of the airbridges and a corresponding portion of the second insulating layer to adhere the corresponding portion of the second insulating layer to the portion of each of the airbridges, wherein the portion of each of the airbridges and the corresponding portion of the second insulating layer includes at least a portion of sidewalls of the opening defined by the airbridges.

11. The semiconductor device of claim 10, wherein the airbridges extend over portions of the corresponding air space.

12. A semiconductor device, comprising:

a device pattern formed on a semiconductor substrate;

a seed layer formed on the device pattern;

a first airbridge formed on the seed layer comprising a plated conductive material;

a second airbridge formed on the seed layer comprising a plated conductive material, wherein the first airbridge and the second airbridge are separated by an opening and a corresponding air space, defined by the first airbridge and the second airbridge, at least a portion of the device pattern being positioned within the corresponding air space;

an adhesion layer formed on each of the first airbridge and the second airbridge, extending over at least a portion of sidewalls of the opening separating the first airbridge and the second airbridge; and

an insulating layer formed on the adhesion layer on each of the first airbridge and the second airbridge, such that the adhesion layer is between the insulating layer and each of the first airbridge and the second airbridge, including on the adhesion layer extending over the at least a portion of the sidewalls of the opening, wherein the adhesion layer adheres the insulating layer to the plated conductive material of the first airbridge and the second airbridge.

13. The device of claim 12, wherein each plated conductive material comprises gold and the insulating layer comprises silicon nitride.

14. The device of claim 13, wherein the adhesion layer comprises a conductive adhesion material.

15. The device of claim 13, wherein the seed layer comprises plated gold.

16. The device of claim 12, wherein the semiconductor device comprises a transistor formed on the semiconductor substrate, the transistor comprising a gate, a source and a drain.

17. The device of claim 16, wherein the first airbridge extends from a source electrode electrically connected to the source of the transistor, and the second airbridge extends from a drain electrode electrically connected to the drain of the transistor.