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Circuit and method for eliminating shutdown after-image, and display device

  • US 9,865,204 B2
  • Filed: 09/13/2013
  • Issued: 01/09/2018
  • Est. Priority Date: 07/23/2013
  • Status: Active Grant
First Claim
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1. A circuit for eliminating a shutdown after-image, comprising:

  • a control module, configured to apply a common voltage of a liquid crystal panel to a gate line of the liquid crystal panel under control of a shutdown signal when the liquid crystal panel is shut down;

    wherein the control module comprises;

    a first switch unit, configured to output a multi-level gate voltage MLG to the gate line during operation of the liquid crystal panel; and

    a second switch unit, configured to output the common voltage to the gate line when the liquid crystal panel is shut down; and

    a third switch unit, configured to supply power to a gate driving circuit by using the common voltage when the liquid crystal panel is shut down;

    wherein the first switch unit is an N-type MOSFET, a gate electrode of the first switch unit is configured to receive the shutdown signal, a source electrode of the first switch unit is coupled to an MLG output end, and a drain electrode of the first switch unit is coupled to a voltage input end of the gate line;

    wherein the second switch unit is a P-type MOSFET, a gate electrode of the second switch unit is configured to receive the shutdown signal, a source electrode of the second switch unit is coupled to a common voltage output end, and a drain electrode of the second switch unit is coupled to a voltage input end of the gate line; and

    wherein the third switch unit is a P-type MOSFET, a gate electrode of the third switch unit is configured to receive the shutdown signal, the gate electrode of the third switch unit is coupled to the gate electrode of the first switch unit and the gate electrode of the second switch unit, a source electrode of the third switch unit is coupled to the common voltage output end, and a drain electrode of the third switch unit is coupled to a power voltage input end of the gate driving circuit.

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