Semiconductor device and structure
First Claim
Patent Images
1. An Integrated Circuit device, comprising:
- a base wafer comprising single crystal, said base wafer comprising a plurality of first transistors;
at least one metal layer providing interconnection between said plurality of first transistors; and
a second layer of greater than 5 nm and less than 2 micron thickness, said second layer comprising a plurality of second single crystal transistors, said second layer overlying said at least one metal layer;
a first conductive grid underneath said second layer, said first conductive grid is constructed to provide power to at least one of said plurality of first transistors; and
a second conductive grid overlaying said second single crystal transistors, said second conductive grid is constructed to provide power to at least one of said plurality of second transistors;
wherein said second conductive grid has a substantially higher current conduction capacity than said first conductive grid.
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Abstract
An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between the plurality of first transistors; and a second layer of less than 2 micron thickness, the second layer including a plurality of second single crystal transistors, and the second layer overlying the at least one metal layer; wherein the material composition of at least one of the plurality of second single crystal transistors is substantially different than the material composition of at least one of the plurality of first transistors.
672 Citations
20 Claims
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1. An Integrated Circuit device, comprising:
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a base wafer comprising single crystal, said base wafer comprising a plurality of first transistors; at least one metal layer providing interconnection between said plurality of first transistors; and a second layer of greater than 5 nm and less than 2 micron thickness, said second layer comprising a plurality of second single crystal transistors, said second layer overlying said at least one metal layer; a first conductive grid underneath said second layer, said first conductive grid is constructed to provide power to at least one of said plurality of first transistors; and a second conductive grid overlaying said second single crystal transistors, said second conductive grid is constructed to provide power to at least one of said plurality of second transistors; wherein said second conductive grid has a substantially higher current conduction capacity than said first conductive grid. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An Integrated Circuit device, comprising:
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a base wafer comprising single crystal, said base wafer comprising a plurality of first transistors; at least one metal layer providing interconnection between said plurality of first transistors; a second layer of greater than 5 nm and less than 2 micron thickness, said second layer comprising a plurality of second single crystal transistors, said second layer overlying said at least one metal layer; a first conductive grid underneath said second layer, said first conductive grid is constructed to provide power to at least one of said plurality of first transistors; and a second conductive grid overlaying said second single crystal transistors, said second conductive grid is constructed to provide power to at least one of said plurality of second transistors; wherein said second conductive grid has a substantially higher current conduction capacity than said first conductive grid, and wherein said second layer comprises a wireless structure providing wireless communication between said device and external devices. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. An Integrated Circuit device, comprising:
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a base wafer comprising single crystal, said base wafer comprising a plurality of first transistors; at least one metal layer providing interconnection between said plurality of first transistors; a second layer of greater than 5 nm and less than 2 micron thickness, said second layer comprising a plurality of second single crystal transistors, said second layer overlying said at least one metal layer; wherein said second layer comprises SerDes circuits, and a first conductive grid underneath said second layer, said first conductive grid is constructed to provide power to at least one of said plurality of first transistors; a second conductive grid overlaying said second single crystal transistors, said second conductive grid is constructed to provide power to at least one of said plurality of second transistors, wherein said second conductive grid has a substantially higher current conduction capacity than said first conductive grid; and a connection path between at least one of said second transistors and at least one of said first transistors, wherein said connection path comprises a through said second layer via with a diameter of 150 nm or less. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification