Structure and process to tuck fin tips self-aligned to gates

• US 9,876,074 B2
• Filed: 05/22/2015
• Issued: 01/23/2018
• Est. Priority Date: 05/22/2015
• Status: Active Grant

• Current Assignee: Tessera (Adeia Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Doris, Bruce B., He, Hong, Kanakasabapathy, Sivananda K., Karve, Gauri, Lie, Fee Li, Liu, Derrick, Seo, Soon-Cheon, Sieg, Stuart A.
• Primary Examiner(s): Lee, Cheung
• Assistant Examiner(s): Smith, Stephen C
• Application Number:
  US14/719,829
• Publication Number:
  US 20160343861A1
• Time in Patent Office: 977 Days
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.

Claims

1. A semiconductor structure comprising:

a semiconductor fin portion having an end wall and extending upwards from a substrate;

a gate structure straddling a portion of said semiconductor fin portion;

a first set of gate spacers located on opposing sidewall surfaces of said gate structure; and

a second set of gate spacers located on outer sidewalls of said first gate spacers, wherein one gate spacer of said second set of gate spacers has an inner sidewall surface having an upper portion directly contacting said outer sidewall of one of said gate spacers of said first set of gate spacers and a lower portion directly contacting and covering an entirety of a sidewall of said end wall of said semiconductor fin portion.

2. The semiconductor structure of claim 1, wherein said gate structure is a functional gate structure.

3. The semiconductor structure of claim 2, wherein each gate spacer of said first set of gate spacers is only located on a topmost surface of said semiconductor fin portion, and wherein one gate spacer of said first set of gate spacers has an outer edge that is vertically aligned to said sidewall of said end wall of said semiconductor fin portion.

4. The semiconductor structure of claim 3, wherein another gate spacer of said second set of gate spacers straddles over said topmost surface of said semiconductor fin portion.

5. The semiconductor structure of claim 2, wherein each gate spacer of said first set of gate spacers straddles over said semiconductor fin portion.

6. The semiconductor structure of claim 5, wherein another gate spacer of said second set of gate spacers straddles another portion of said semiconductor fin portion.

7. The semiconductor structure of claim 1, wherein said substrate is an insulator layer.

8. The semiconductor structure of claim 1, wherein said first set of gate spacers comprises a same dielectric material as said second set of gate spacers.

9. The semiconductor structure of claim 1, wherein said first set of gate spacers comprise a different dielectric material than said second set of gate spacers.

10. The semiconductor structure of claim 1, wherein at least one gate spacer of said first set of gate spacers or said second set of gate spacers is composed of a SiBCN or SiOCN material.

11. The semiconductor structure of claim 1, wherein one gate spacer of said first set of gate spacers has an outer surface that is vertically aligned with said sidewall surface of said end wall of said semiconductor fin portion.

12. The semiconductor structure of claim 1, wherein a bottommost surface of each gate spacer of said second set of gate spacers is coplanar with a bottommost surface of said semiconductor fin portion.