Pixel of a multi-stacked CMOS image sensor and method of manufacturing the same

• US 9,899,453 B2
• Filed: 02/01/2016
• Issued: 02/20/2018
• Est. Priority Date: 02/01/2011
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Kyung-bae, Kim, Kyu-sik, Jin, Yong-wan, Choi, Woong, Lee, Kwang-hee, Kim, Do-hwan
• Primary Examiner(s): Chen, Yu
• Application Number:
  US15/012,604
• Publication Number:
  US 20160225827A1
• Time in Patent Office: 750 Days
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14647 Multicolour imagers having a stacked pixel-element structure, e.g. npn, npnpn or MQW elements
• CPC Class Codes: H01L 27/14667 Colour imagers
• CPC Class Codes: H01L 27/14685 Process for coatings or optical elements
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 33/08 with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body H01L27/15 takes precedence
• CPC Class Codes: H10K 39/32 Organic image sensors

Abstract

Provided is a pixel of a multi-stacked complementary metal-oxide semiconductor (CMOS) image sensor and a method of manufacturing the image sensor including a light-receiving unit that may include first through third photodiode layers that are sequentially stacked, an integrated circuit (IC) that is formed below the light-receiving unit, electrode layers that are formed on and below each of the first through third photodiode layers, and a contact plug that connects the electrode layer formed below each of the first through third photodiode layers with a transistor of the IC.

Claims

1. A method of manufacturing a pixel of a multi-stacked complementary metal-oxide semiconductor (CMOS) image sensor, the method comprising:

forming a lower insulating layer on an integrated circuit (IC);

forming a first contact hole in the lower insulating layer to expose a first transistor of the IC;

forming a first lower electrode layer on the lower insulating layer to fill the first contact hole;

sequentially stacking a first photodiode layer and a first upper electrode layer on the first lower electrode layer to be separate from the first contact hole, wherein a width of the first lower electrode layer is larger than a width of the first photodiode layer and a width of the first upper electrode layer;

forming a first interlayer insulating layer to cover the first lower electrode layer, and extend beyond the width of the first photodiode layer, and the width of the first upper electrode layer;

forming a second contact hole penetrating through the first interlayer insulating layer and the lower insulating layer, and exposing a second transistor of the IC;

forming a second lower electrode layer on the first interlayer insulating layer to fill the second contact hole;

sequentially stacking a second photodiode layer and a second upper electrode layer on the second lower electrode layer to be separate from the second contact hole;

forming a second interlayer insulating layer to cover the second lower electrode layer, the second photodiode layer, and the second upper electrode layer;

forming a third contact hole penetrating through the second interlayer insulating layer, the first interlayer insulating layer, and the lower insulating layer, and exposing a third transistor of the IC;

forming a third lower electrode layer on the second interlayer insulating layer to fill the third contact hole;

sequentially stacking a third photodiode layer and a third upper electrode layer on the third lower electrode layer to be separate from the third contact hole; and

forming an upper insulating layer to cover the third lower electrode layer, the third photodiode layer, and the third upper electrode layer.

2. The method of claim 1, wherein the forming of the first lower electrode layer comprises:

forming a first contact plug that fills the first contact hole; and

forming the first lower electrode layer on the lower insulating layer to contact the first contact plug.

3. The method of claim 1, wherein the forming of the second lower electrode layer comprises:

forming a second contact plug that fills the second contact hole; and

forming the second lower electrode layer on the first interlayer insulating layer to contact the second contact plug.

4. The method of claim 1, wherein the forming of the third lower electrode layer comprises:

forming a third contact plug that fills the third contact hole; and

forming the third lower electrode layer on the second interlayer insulating layer to contact the third contact plug.

5. The method of claim 1, wherein the forming of the first contact hole further comprises forming another contact hole to expose a portion of the IC in a region of the lower insulating layer that is separate from the first contact hole.

6. The method of claim 5, wherein the forming of the first lower electrode layer comprises filling the other contact hole with the first lower electrode layer.

7. The method of claim 1, wherein the forming of the second contact hole further comprises forming another contact hole to expose a portion of the IC in a region of the first interlayer insulating layer that is separate from the second contact hole.

8. The method of claim 7, wherein the forming of the second lower electrode layer comprises filling the other contact hole with the second lower electrode layer.

9. The method of claim 1, wherein the forming of the third contact hole further comprises forming another contact hole to expose a portion of the IC in a region of the second interlayer insulating layer that is separate from the third contact hole.

10. The method of claim 9, wherein the forming of the third lower electrode layer comprises filling the other contact hole with the third lower electrode layer.

11. The method of claim 1, wherein each of the first through third photodiode layers comprises at least one of an organic semiconductor layer, a crystal silicon layer, an amorphous silicon layer, a CIGS layer, and a quantum dot layer.

12. The method of claim 1, wherein the forming the first interlayer insulating layer comprises extending the first interlayer insulating layer to extend beyond a width of the first lower electrode layer, the width of the first photodiode layer, and the width of the first upper electrode layer on both sides.

13. The method of claim 1, wherein the forming the first lower electrode layer comprises extending the first lower electrode layer beyond the width of the first photodiode layer, and the width of the first upper electrode layer.

14. The method of claim 1, wherein the forming the first lower electrode layer comprises extending, on only one side, the first lower electrode layer beyond the width of the first photodiode layer, and the width of the first upper electrode layer.

15. The method of claim 1, wherein the forming the second contact hole comprises forming the second contact hole to a side of and separate from the first lower electrode layer, the first photodiode layer, and the first upper electrode layer, without the second contact hole passing through the first lower electrode layer, the first photodiode layer, and the first upper electrode layer.

16. The method of claim 1, wherein the forming the third contact hole comprises forming the third contact hole to a side of the first lower electrode layer, the first photodiode layer, the first upper electrode layer, the second lower electrode layer, the second photodiode layer, and the second upper electrode layer, without the third contact hole passing through the first lower electrode layer, the first photodiode layer, the first upper electrode layer, the second lower electrode layer, the second photodiode layer, and the second upper electrode layer.

17. The method of claim 1, wherein the forming the lower insulating layer comprises forming the lower insulating layer directly above the first transistor of the IC.

18. The method of claim 1, wherein the forming the second upper electrode layer comprises forming the second upper electrode layer using a different material from the first upper electrode layer.

19. The method of claim 1, wherein the forming the third upper electrode layer comprises forming the third upper electrode layer using a different material from the first upper electrode layer.

20. The method of claim 1, wherein the forming the upper insulating layer comprises forming the upper insulating layer using a different material from the lower insulating layer.