Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions

  • US 9,905,691 B2
  • Filed: 02/19/2016
  • Issued: 02/27/2018
  • Est. Priority Date: 08/12/2002
  • Status: Active Grant
First Claim
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1. A structure, comprising a semiconductor region in a substrate, a metal electrical contact to said semiconductor region, and a passivating dielectric tunnel barrier layer between said semiconductor region and said metal electrical contact, said semiconductor region being electrically connected to said metal electrical contact through said passivating dielectric tunnel barrier layer, wherein said passivating dielectric tunnel barrier layer comprises a metal oxide and a semiconductor oxide.

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