Clock generation circuit that tracks critical path across process, voltage and temperature variation

• US 9,912,322 B2
• Filed: 09/12/2016
• Issued: 03/06/2018
• Est. Priority Date: 07/03/2013
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Bollapalli, Kalyana, Raja, Tezaswi
• Primary Examiner(s): Johnson, Ryan
• Application Number:
  US15/263,127
• Publication Number:
  US 20160380619A1
• Time in Patent Office: 540 Days
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: G01R 31/31727 Clock circuits aspects, e.g. test clock circuit details, timing aspects for signal generation, circuits for testing clocks G01R31/31725 takes precedence; concerning scan test G01R31/318552, for tester hardware G01R31/31922
• CPC Class Codes: H03K 19/21 EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
• CPC Class Codes: H03K 2005/00019 Variable delay
• CPC Class Codes: H03K 3/011 Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature to maintain energy constant H03K3/015
• CPC Class Codes: H03K 3/0315 Ring oscillators

Abstract

Clock generation circuit that track critical path across process, voltage and temperature variation. In accordance with a first embodiment of the present invention, an integrated circuit device includes an oscillator electronic circuit on the integrated circuit device configured to produce an oscillating signal and a receiving electronic circuit configured to use the oscillating signal as a system clock. The oscillating signal tracks a frequency-voltage characteristic of the receiving electronic circuit across process, voltage and temperature variations. The oscillating signal may be independent of any off-chip oscillating reference signal.

Claims

1. An integrated circuit device including a clock generator circuit, the clock generator circuit comprising:

a plurality of independently tunable delay chains, comprising;

a first independently tunable delay chain having an output and comprising first delay elements specific to the first independently tunable delay chain, and

a second independently tunable delay chain having an output and comprising second delay elements specific to the second independently tunable delay chain; and

combining circuitry configured to combine the outputs of the plurality of independently tunable delay chains to generate an output of the clock generator circuit.

2. The integrated circuit device of claim 1 wherein said combining circuitry comprises a coincidence detector.

3. The integrated circuit device of claim 2 wherein said coincidence detector comprises a Mueller-C gate.

4. The integrated circuit device of claim 1 wherein said second delay elements are configured to perform a different digital function than said first delay elements.

5. The integrated circuit device of claim 1 wherein said first independently tunable delay chain is free of internal feedback.

6. The integrated circuit device of claim 1 wherein said first independently tunable delay chain further comprises a plurality of selectable drivers coupled in parallel with one or more other elements of said first independently tunable delay chain, configured to aid signal transitions within said first independently tunable delay chain when enabled.

7. The integrated circuit device of claim 6 wherein each of said plurality of selectable drivers is independently enabled.

8. The integrated circuit device of claim 1 wherein each of said plurality of independently tunable delay chains comprises a plurality of fine tuning stages, wherein each of said fine tuning stages comprises a main delay stage, configured to be always on, coupled in parallel with a respective selectable driver.

9. The integrated circuit device of claim 8 wherein each of said plurality of selectable drivers is independently enabled.

10. The integrated circuit device of claim 8 wherein a delay of each said plurality of fine tuning stages is configured to be different from a respective delay of each other fine tuning stage.

11. The integrated circuit device of claim 8 wherein said output of the clock generator circuit is independent of any off-chip oscillating reference signal.

12. An integrated circuit device including a clock generator circuit, the clock generator circuit comprising:

a plurality of independently tunable delay chains, including;

a first independently tunable delay chain having an output and comprising first delay elements specific to the first independently tunable delay chain, and

a second independently tunable delay chain having an output and comprising second delay elements specific to the second independently tunable delay chain,

wherein the first and second delay elements each model delays due to a different circuit element type, the circuit element type selected from the set consisting of wires, simple gates, complex gates and complex cells; and

combining circuitry configured to combine the outputs of the plurality of independently tunable delay chains to generate an output of the clock generator circuit.

13. The integrated circuit device of claim 12 wherein said combining circuitry comprises a coincidence detector.

14. The integrated circuit device of claim 12 wherein said coincidence detector comprises a Mueller-C gate.

15. The integrated circuit device of claim 12 wherein said first independently tunable delay chain further comprises a plurality of selectable drivers coupled in parallel with one or more other elements of said first independently tunable delay chain, configured to aid signal transitions within said first independently tunable delay chain when enabled.

16. A method comprising:

generating a first delay signal by a first independently tunable delay chain having an output and comprising first delay elements specific to the first independently tunable delay chain;

generating a second delay signal by a second independently tunable delay chain having an output and comprising first delay elements specific to the second independently tunable delay chain; and

combining the outputs of the first and second independently tunable delay chains to generate a clock signal that oscillates at a frequency corresponding to the slower of the first and second delay signals.

17. The method of claim 16 wherein said combining utilizes a Mueller-C gate.

18. The method of claim 16 further comprising selectively enabling a plurality of selectable drivers coupled in parallel with one or more other elements of said first and second independently tunable delay chains to speed up a signal transition of said first or said second delay signals.

19. The method of claim 16 wherein said generating utilizes a ring oscillator.

20. The method of claim 16 wherein the first and second delay elements each model delays due to a different circuit element type, the circuit element type selected from the set consisting of wires, simple gates, complex gates and complex cells.

21. An integrated circuit device including a clock generator circuit, the clock generator circuit comprising:

a plurality of independently tunable delay chains, comprising;

a first independently tunable delay chain having an output and comprising first type delay elements, and

a second independently tunable delay chain having an output and comprising second type delay elements,

wherein the first and second type delay elements are different; and

combining circuitry configured to combine the outputs of the plurality of independently tunable delay chains to generate an output of the clock generator circuit.

22. The integrated circuit device of claim 21 wherein said combining circuitry comprises a coincidence detector.

23. The integrated circuit device of claim 21 wherein said second type delay elements are configured to perform a different digital function than said first type delay elements.

24. The integrated circuit device of claim 21 wherein said first independently tunable delay chain is free of internal feedback.

25. The integrated circuit device of claim 21 wherein said first independently tunable delay chain further comprises a plurality of selectable drivers coupled in parallel with one or more other elements of said first independently tunable delay chain, configured to aid signal transitions within said first independently tunable delay chain when enabled.

26. The integrated circuit device of claim 25 wherein each of said plurality of selectable drivers is independently enabled.

27. The integrated circuit device of claim 21 wherein each of said plurality of independently tunable delay chains comprises a plurality of fine tuning stages, wherein each of said fine tuning stages comprises a main delay stage, configured to be always on, coupled in parallel with a respective selectable driver.

28. The integrated circuit device of claim 27 wherein each of said plurality of selectable drivers is independently enabled.

29. A method comprising:

generating a first delay signal by a first independently tunable delay chain having an output and comprising first type delay elements;

generating a second delay signal by a second independently tunable delay chain having an output and comprising second type delay elements,

wherein the first and second type delay elements are different; and

combining the outputs of the first and second independently tunable delay chains to generate a clock signal that oscillates at a frequency corresponding to the slower of the first and second delay signals.

30. The method of claim 29 wherein said combining utilizes a Mueller-C gate.

31. The method of claim 29 further comprising selectively enabling a plurality of selectable drivers coupled in parallel with one or more other elements of said first and second type independently tunable delay chains to speed up a signal transition of said first or said second delay signals.

32. The method of claim 29 wherein said generating utilizes a ring oscillator.

33. The method of claim 29 wherein the first and second type delay elements each model delays due to a different circuit element type, the circuit element type selected from the set consisting of wires, simple gates, complex gates and complex cells.